Modeling the Global Critical Path of Highly Concurrent Systems

Tuesday February 21, 2006
Hamerschlag Hall D-210
4:30 pm

Girish Venkataramani
Carnegie Mellon University

Architectural optimizations of hardware designs rely intrinsically on a reliable timing analysis framework. Traditionally, timing analysis has focused on analyzing the critical path of the combinational DAGs between clocked registers, with the aim of determining the minimum clock period under a slew of constraints. The Global Critical Path (GCP), on the other hand, highlights a path that transcends state-holding elements in a circuit graph, which may contain cycles. This path highlights the circuit components that are responsible for the end-to-end execution delay, and are therefore prime candidates for optimization.

In this talk, I will describe a formal framework for the timing analysis of asynchronous circuits, using which the GCP of the circuit is accurately constructed. Knowledge of the GCP provides valuable insights not only for the design under consideration, but also for the design methodology itself. I will demonstrate how this knowledge is used in the formulation of certain interesting optimizations. This analysis and optimization loop is fully automated and has been incorporated into the CASH synthesis system. Finally, I will also show, using a microprocessor as an example, how these concepts can be applied to synchronous circuits as well.

As a Phd candidate, Girish has been spending the last few years deconstructing the nature of asynchronous circuits, in order to construct highly optimized ones, within the automated CASH synthesis system. He is interested in hardware compilation, timing analysis of asynchronous circuits, and system architecture of specialized reconfigurable fabrics. He is part of the Phoenix team supervised by his adviser, Seth Goldstein.