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Temporal Memory Streaming

Tuesday February 20, 2007
Hamerschlag Hall D-210
4:30 pm

Thomas Wenisch
Carnegie Mellon University

While semiconductor scaling has steadily improved processor performance, scaling trends in memory technology have favored improving density over access latency. Because of this processor/memory performance gap—often called the memory wall—modern server processors spend over half of execution time stalled on long-latency memory accesses. To improve average memory response time for existing software, architects must design mechanisms that issue memory requests earlier and with greater parallelism. Commercial server applications present a particular challenge for memory system design because their large footprints, complex access patterns, and frequent chains of dependent misses are not amenable to existing approaches for hiding memory latency. Despite their complexity, these applications nonetheless execute repetitive code sequences, which give rise to recurring access sequences—a phenomenon I call temporal correlation. In this talk, I present Temporal Memory Streaming, a memory system design paradigm where hardware mechanisms observe repetitive access sequences at runtime and use recorded sequences to stream data from memory in parallel and in advance of explicit requests.

Tom Wenisch is completing his Ph.D. in Electrical and Computer Engineering at Carnegie Mellon University this spring, specializing in computer architecture.

Tom's current research includes memory streaming, multiprocessor memory system design and computer system performance evaluation. His future research will focus on multi-core/multiprocessor systems, with particular emphasis on improving system programmability and debuggability.


Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science