Intra-chip Memory Streaming

Tuesday February 12, 2008
Hamerschlag Hall D-210
4:00 pm

Mike Ferdman
Carnegie Mellon University

Chip multiprocessors (CMPs) are continuing to scale in number of cores and aggregate on-chip cache capacity. Although overall cache capacity is increasing, access latency constraints preclude increasing L1 cache size. Hence, L1 cache misses satisfied on chip are becoming a critical performance bottleneck in CMPs.

In this talk I will describe Intra-chip Memory Streaming (IMS)—a mechanism for prefetching address-correlated instruction and data streams from L2 and peer L1 caches—to hide the latency of on-chip accesses. I will present an analysis of L1 cache misses of commercial applications in CMP systems, and demonstrate why IMS can leverage these results to improve performance of a CMP.

Mike is a fourth year PhD candidate in the Computer Architecture Laboratory at Carnegie Mellon, where he is advised by Prof. Babak Falsafi. Mike's research interests include processors and the software that runs on them. His work has primarily been devoted to finding ways to improve processor performance through hiding the latency of modern memory systems.