Link to CALCM Home  

Towards a power efficient trace-cache based microarchitecture

February 12, 2002 Tuesday
Hamerschlag Hall 1112
4:00 p.m.

Emil Talpes

Carnegie Mellon University

Power consumption has recently become one of the limiting factors in designing high performance processors. While superscalar processors become faster and wider, the increasing clock rate and transistor count of today's microarchitectures cause greater problems with power consumption and heat dissipation. In order to solve this problem for future generation of CPUs, we have to investigate technology solutions such as voltage reduction (that comes with feature scaling) as well as architecture solutions.
This work investigates the second alternative and proposes a new superscalar, out-of-order microarchitecture, specially designed to reduce the power consumption. More precisely, we show that by modifying the well-established superscalar processor architecture, significant gains can be achieved in terms of power requirements without significant performance penalty. Our approach aims to limiting the growing amount of power used in a typical processor for dynamic optimizations. We try to achieve that by reusing as much as possible from the work done by the front-end of a typical superscalar, out-of-order pipeline via the use of a cache nested deeply into the processor structure.

Emil Talpes obtained his BS in Computer Science from the Polytechnic Institute of Bucharest (Romania) in 1999 and he iscurrently enrolled as a Ph.D. student in the ECE Department at CMU, working with Prof. Diana Marculescu.



Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science