PROTOFLEX:
Co-Simulation for Component-wise FPGA Emulator Development
Tuesday January 31, 2006
Hamerschlag Hall D-210
4:00 pm
This is a practice talk for our paper in the Workshop
for Architecture Research using FPGA Platforms at the 12th Annual
International Symposium on High-Performance Computer Architecture.
Eric
Chung
Carnegie Mellon University
Surging interest in developing large-scale, FPGA-based full-system
multiprocessor emulators faces the challenge of verifying and composing
multiple, potentially untrustworthy RTL components. In this talk
I describe PROTOFLEX, a hardware/software co-simulation methodology
to facilitate systematic development of RTL components. I then describe
experiences using the PROTOFLEX methodology to develop the RTL model
of a microprogrammable protocol engine for directory-based cache-coherence.
Eric S. Chung is a second-year PhD student advised by Professor
James C. Hoe in Electrical and Computer Engineering at Carnegie
Mellon University. He received his B.S. in EECS from the University
of California Berkeley. His research interests are designing and
prototyping scalable, reliable server architectures and transactional
memory.
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