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Improving the Simulation and Programmability of Future Multiprocessor Systems

Tuesday January 30, 2007
Hamerschlag Hall D-210
4:30 pm

Thomas Wenisch
Carnegie Mellon University

The demand for computer system performance continues to grow to enable solutions to previously infeasible computing problems. In the past, microarchitectural innovations and processor frequency scaling have yielded exponential system performance improvement. However, challenges in microprocessor design complexity, verification, scalability, and power dissipation have driven the semiconductor industry to bet on multi-core/multiprocessor systems as the primary avenue for continued performance scaling.

Unfortunately, the multiprocessor paradigm creates many new challenges for the system designer. In this talk, I present research done at Carnegie Mellon University to address two such challenges: rapid system performance evaluation and improving multiprocessor system programmability. Because hardware availability lags behind system design efforts, designers frequently must resort to software simulation to evaluate future system performance. Unfortunately, detailed simulation of a uniprocessor system is already four orders of magnitude slower than actual hardware, and simulation time grows at least linearly with the number of processors. In the first portion of my talk, I present a rigorous statistical sampling methodology that makes simulation-based studies of commercial software applications and realistic system sizes tractable while providing quantified measures of statistical confidence with each estimated performance metric. Maximizing the performance of multiprocessor shared-memory applications is challenging because programmers must often write code that obeys arcane and unintuitive rules of relaxed memory consistency models. In the second portion of my talk, I show that, contrary to conventional wisdom, multiprocessors can provide the simpler programming model of a strongly-ordered memory system while matching or exceeding the performance under more relaxed memory consistency models.

Tom Wenisch is completing his Ph.D. in Electrical and Computer Engineering at Carnegie Mellon University this spring, specializing in computer architecture under Prof. Babak Falsafi. Tom's past research focuses on stream-based prefetching, multiprocessor memory system design and computer system performance evaluation. His future research interests center on extending the historic trend of exponential computer system performance improvement into the multi-core era.


Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science