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Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay


January 29, 2002 Tuesday
Hamerschlag Hall 1112
4:30 p.m.

Se-Hyun Yang

Carnegie Mellon University

Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requirement variability in applications to reduce cache size and eliminate energy dissipation in the cache's unused sections with minimal impact on performance.
In this talk, I will compare and contrast the proposed design choices for resizable caches and evaluate the effectiveness of cache resizings in reducing the overall energy-delay in deep-submicron processors. In addition, I propose a new resizable cache organization and investigate the energy savings from resizing d-cache and i-cache together.

Se-Hyun Yang is now pursuing his doctoral degree in department of Electrical and Computer Engineering at Carnegie Mellon University. He received his B.S. and M.S. from Korea Advanced Institute of Science and Technology. His current research interests focus on Computer Architecture, especially on power-aware microprocessor and memory system design.



Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science