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Improving Superscalar Efficiency with Mini-Graph Processing

Friday January 19, 2007
Hamerschlag Hall 1112
11:00 am

Anne Bracy
University of Pennsylvania

For decades, performance has driven the direction of computer development. In recent years, however, secondary design constraints -- power, area, and temperature, to name a few -- that are often at odds with performance have become increasingly important. For example, the performance-driven trend of placing increasingly many cores on one chip demands that each core have more modest power consumption. Even in the multi-core paradigm, however, single-thread performance is still critically important. Power constraints have simply turned the quest for performance into the quest for performance/power efficiency.

This talk introduces mini-graph processing, a technique that improves the performance efficiency of any superscalar processor. Mini-graphs are compiler-detected aggregates of multiple instructions that look and behave like singleton instructions throughout the entire pipeline. A mini-graph processor exploits instruction fusion to increase the efficiency of pipeline stages and structures that perform instruction book-keeping. A superscalar processor enhanced with mini-graphs can match the performance otherwise achieved with a wider, deeper superscalar processor. It does so in a more efficient manner: maintaining smaller superscalar structures, supporting a higher clock rate, and consuming less energy.

In this talk, I will introduce the concept of mini-graphs, describe the basic architecture of a mini-graph processor, and discuss static and dynamic intelligent mini-graph selection algorithms.

Anne Bracy is a doctoral candidate in the Computer and Information Science department at the University of Pennsylvania. She researches novel approaches to efficient superscalar design. Prior to her doctoral studies, Anne was an undergraduate student at Stanford University. Anne has also been a member of Intel's Microarchitecture Research Lab in Santa Clara, California since 2005.


Department of Electrical and Computer EngineeringCarnegie Mellon UniversitySchool of Computer Science