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        <dc:date>2012-05-14T13:00:25-04:00</dc:date>
        <dc:creator>HanBin Yoon</dc:creator>
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        <description>Thursday May 24, 2012

CIC 4th floor Panther Hollow

12:00 pm




Samira Khan (CS, UT San Antonio)


Abstract

Improvements in CMOS process technology have resulted in faster processors in each generation for the last several decades. The current trend is to increase core count to achieve higher throughput.  However, this focus limits the performance of single-threaded workloads. At the same time, power constraints are limiting the number of transistors that can be active at a given time.  We ca…</description>
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        <dc:date>2012-05-14T12:59:43-04:00</dc:date>
        <dc:creator>HanBin Yoon</dc:creator>
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        <description>The CALCM seminar series is a weekly meeting of faculty and students with broad interests in Computer Architecture, and is open to all. The seminar is an excellent medium for CALCM students/faculty to present their recent research results and/or practice conference presentations, for students to polish their presentation skills and present external results from recent conferences, and for outside speakers to tell us about their work.</description>
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        <dc:date>2012-02-15T23:24:18-04:00</dc:date>
        <dc:creator>HanBin Yoon</dc:creator>
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        <description>Wednesday Feb. 29, 2012

Hamerschlag Hall D-210

4:00 pm




Ioan Stefanovici (CS, Toronto)


Abstract

Main memory is one of the leading hardware causes for machine crashes in today's datacenters. Designing, evaluating and modeling systems that are resilient against memory errors requires a good understanding of the underlying characteristics of errors in DRAM in the field. While there have recently been a few first studies on DRAM errors in production systems, these have been too limited in ei…</description>
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        <dc:date>2012-02-02T15:20:41-04:00</dc:date>
        <dc:creator>HanBin Yoon</dc:creator>
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        <description>Wednesday Feb. 8, 2012

CIC 4th floor Panther Hollow

4:00 pm




Jared Smolens (Oracle)


Abstract

This talk describes the microarchitecture of Oracle's newest processor, the UltraSPARC T4. T4 contains eight out-of-order processing cores that each dynamically support up to 8 threads to provide balanced single- and multi-threaded performance. T4 includes a shared 4 MB L3 cache, two on-chip memory controllers supporting buffered DDR3 memory, two 10 Gb Ethernet controllers, and two x8 PCI-Express…</description>
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        <dc:date>2012-01-21T23:52:04-04:00</dc:date>
        <dc:creator>HanBin Yoon</dc:creator>
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        <description>Wednesday Feb. 22, 2012

Hamerschlag Hall D-210

4:00 pm




Rakesh Kumar (ECE, Illinois)


Abstract

All of computing today relies on an abstraction where software expects the hardware to behave flawlessly for all inputs under all conditions. While the abstraction worked historically due to the relatively small magnitude of variations in hardware and environment, computing will increasingly be done with devices and circuits which are inherently stochastic or whose behavior is stochastic due to …</description>
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