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— seminars:seminar_4_26_16 [2017/09/21 02:02] (current)
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 +====== Automating Performance via Data Layout Transformations and Kernel Code Generation ======
  
 +Tuesday April 26, 2016\\
 +Location: CIC Panther Hollow Room\\
 +Time: 4:30PM\\
 +
 +
 +{{:​seminars:​richard_veras.png?​256|}}\\
 +
 +**Richard Veras (Carnegie Mellon University)**\\
 +
 +
 +
 +===== Abstract =====
 +
 +Graph computations are ubiquitous in Scientific Computing, Data-Analytics,​ and Machine Learning. Because of their significance and the  desire to compute on larger data-set, we want high performance implementations of these graph operations. Unfortunately,​ the performance of even state-of-the-art implementations fall short of the performance seen by Dense Linear Algebra and Structured Mesh computations because the irregular sparse structure of real world graphs do not map well to modern hardware.
 +
 +To ameliorate this issue existing work falls into two categories: Data-Driven and Sparse Linear Algebra based frameworks. The data-driven libraries take advantage of the structure of the graph at run-time to expose parallelism at the expense of high overhead. Whereas the Sparse Linear Algebra frameworks cast the problem in terms of more efficient sparse matrix operations, they do so at the expense of losing structural information of the graph. My proposed work intends to reconcile the two approaches for certain classes of graphs that admit an underlying structure. This will be done by utilizing this underlying structure in these graphs to enable the types of optimizations used for Dense Linear Algebra and Structured Mesh computations.
 +
 +===== Bio =====
 +Richard Veras is a fifth year PhD Student in the Electrical and Computer Engineering Department at Carnegie Mellon University. He is a member of the SPIRAL group and is being advised by Dr. Franz Franchetti. He earned his bachelors in Computer Science and Mathematics at the University of Texas at Austin and his research interests are in Automatic Program Generation, and Scientific and High Performance Computing.