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| + | ====== Selectively Consistent Approximate Parallel Execution ====== | ||
| + | Friday March 24, 2017\\ | ||
| + | Location: CIC Panther Hollow Room\\ | ||
| + | Time: 4:30PM\\ | ||
| + | |||
| + | **Vignesh Balaji (CMU)**\\ | ||
| + | |||
| + | =====Abstract===== | ||
| + | Programmers writing shared memory parallel applications use synchronization | ||
| + | operations for correct manipulation of shared data. They also rely on hardware | ||
| + | based cache coherence to automatically transport data between cores. While | ||
| + | synchronization and cache coherence are required for correct execution of | ||
| + | parallel applications, they impose a significant performance penalty. The | ||
| + | serialization and data movement overheads of these operations impact | ||
| + | scalability of parallel applications. Research in approximate computing has | ||
| + | demonstrated the error tolerance of many important application domains by | ||
| + | improving performance with minimal impact on output quality. In this talk, I | ||
| + | will present our work on SCAPE - a system that exploits this resilience | ||
| + | towards errors to eliminate synchronization and cache coherence for | ||
| + | performance. Our system allows the programmer to control the quality of such | ||
| + | approximate executions by ensuring precise updates only for program values | ||
| + | deemed quality critical by the programmer. Additionally, SCAPE uses a neural | ||
| + | network to selectively approximate executions only when the expected | ||
| + | performance improvement justifies approximation. Our evaluations show that | ||
| + | SCAPE can improve performance up to 20X while keeping the quality degradation | ||
| + | less than 1% for a collection of graph applications. | ||
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| + | |||
| + | =====Bio===== | ||
| + | Vignesh Balaji is a second year PhD student co-advised by Professors Brandon | ||
| + | Lucia and Radu Marculescu. His research is focused on approximate computing | ||
| + | with a particular emphasis on reducing data movement in multi-core processors. | ||
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| + | \\ | ||
| + | \\ | ||
| + | **[[seminars| Back to the seminar page]]** | ||
