Ever-increasing microarchitectural complexity, through larger caches, core-counts and heterogeneity, has made it increasingly difficult to evaluate next-generation ideas in a timely manner. We have developed Sniper to focus on evaluating these ideas primarily for synchronizing multi-threaded applications and other HPC workloads that put significant stress on today's core and memory hierarchies. In this talk I will discuss two major themes of our work on Sniper. First is the importance of HW/SW co-design for power efficiency, and how taking both HW and SW into account can lead to either higher performance, or more energy efficiency. The in the second half of the talk I will focus on our work in speeding-up simulation of multi-threaded workloads though time-based sampling. Additionally, I will also outline some of the major components and trade-offs made with Sniper that give it its speed and accuracy, as well as allow for detailed program analysis.
Trevor E. Carlson is a PhD student at Ghent University in Belgium. He received his BS and MS degrees from Carnegie Mellon University in 2002 and 2003, respectively. He has previously served as a Staff Engineer at IBM where he helped to author 4 issued patents and also served as a Researcher at IMEC where he investigated efficient architectures for embedded, 3D-stacked systems. He is currently a part of the Intel ExaScience Lab and is the co-author of the Sniper Multi-Core Simulator, a publically available fast and accurate microarchitecture simulator. His research interests include performance modeling and fast and scalable simulation methodologies.