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Tiered-Latency DRAM: Low Latency and Low Cost DRAM Architecture

Tuesday Feb. 14, 2013
Hamerschlag Hall D-210
5:00pm-6:00 pm

Donghyuk Lee (ECE, CMU))

Abstract

The capacity and cost-per-bit of DRAM has historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, such that the performance of systems is often bottlenecked by memory latency.

In this talk, I would like to introduce Tiered-Latency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit. In TL-DRAM, each cell array is split into two smaller segments, allowing one segment to be accessed with low latency without incurring high cost-per-bit. I’ll also introduce mechanisms that use the low-latency segment as a cache for the other segment and show that they improve both performance and energy-efficiency significantly on a wide variety of workloads.

Bio

Donghyuk Lee is a third year PhD stu-dent in the Electrical and Computer Engineering Department at Carnegie Mellon University, working with Professor Onur Mutlu. He received his B.S. in electrical engineering from Seoul National University. He is interested in high-performance and energy-efficient memory subsystems and DNA se-quence analysis.

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