The design of CPUs has always required a balance of performance and efficiency in power, area, and complexity. The emergence of multicore SoCs armed with accelerators for packet processing has shifted this balance from solely single-thread performance to a combination of single-thread performance and efficient parallel processing. This shift requires a new style of core with short and deterministic pipelines, caches and memory systems optimized for low latency and high bandwidth, and an architecture that scales to 48-plus cores on a chip. This talk demonstrates how continuously emerging application demands shaped the fundamental principles behind OCTEON processor cores and supporting on-chip accelerators.
Break-out Session for Students and Advisors: Cavium is building a
community of university and industry partners around the 32-core OCTEON
II solution, with evaluation boards in use by students and professors at
several universities globally. This break-out session for students will
be conducted at the conclusion of the talk above to describe the
evaluation board hardware, the Cavium SDK, and various semester-long
student projects appropriate for upper level undergraduates or first
year masters students. Other aspects of the OCTEON program will be
briefly described, including a multi-university workshop planned in May
for students to present their OCTEON project and compete for the OCTEON
Richard E. Kessler is a Cavium Fellow
and a principal architect of Cavium
processor chips. The Cavium OCTEON and Thunder
product lines are highly-integrated multi-core
processors for intelligent networking, communications,
storage, video, security, and server applications.
Prior to joining Cavium Networks, Richard was a
chip architect in the Digital/Compaq Alpha Group,
and a supercomputer architect at Cray Research.
Dr. Kessler holds a Ph.D. in Computer Architecture
from the University of Wisconsin-Madison, and has
been awarded more than 50 patents.
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