Modern FPGAs contain abundant resources that suggest a potential for being first class computation devices.
However, they are rarely used for computation due to the difficulty involved in using them.
I will present a system that compiles perfect loop nests, common in scientific computing applications, to optimized FPGA implementations.
I’ll discuss how we create parallel designs from sequential code, optimize memory accesses to reduce DRAM bandwidth requirements, and produce compiled designs for either Altera or Xilinx boards.
Gabriel Weisz is a third year PhD student in the Computer Science Department at Carnegie Mellon University, working with Professor James Hoe. He received his B.S. in Computer Science and Electrical Engineering in 1999, and his research interests encompass computer architecture with a focus on FPGA and GPGPU computing.
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