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seminars:seminar_12_11_27 [2012/11/25 13:19]
djuan created
seminars:seminar_12_11_27 [2012/11/25 13:20] (current)
djuan
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=====Abstract===== =====Abstract=====
-An FPGA is a peculiar hardware realization substrate in terms of the relative speed and cost of logic vs. wires vs. memory. In this talk I will present CONNECT, a flexible NoC architecture and RTL generation engine for FPGA-tuned Networks-on-Chip (NoCs). CONNECT embodies a set of design guidelines and disciplines that uniquely influence key NoC design decisions, such as topology, link width, router pipeline depth, network buffer sizing, and flow control and in many cases go against ASIC-driven conventional wisdom in NoC design.  +As NAND flash memory manufacturers scale down to smaller process 
- +technology nodes and store more bits per cell, reliability and endurance 
-Our evaluation shows a significant gain in specializing NoC design decisions to FPGAs' unique mapping and operating characteristics. When compared against a state-of-the-art ASIC-oriented NoC, we obtain similar performance at half the logic resource cost, or alternatively, 3-4x better performance for approximately the same logic resource usage. Our latest results also show great potential for further optimization and fine-tuning of the NoC within an FPGA application by leveraging high-level application knowledge. Finally, in an effort to create a useful research tool for the community, we recently publicly released CONNECT in the form of a flexible user-friendly web-based NoC generator (http://users.ece.cmu.edu/~mpapamic/connect/), which I will demonstrate at the end of the talk. +of flash memory reduce. Wear-leveling 
 +and error correction coding can improve both reliability and endurance, 
 +but finding effective algorithms requires a strong understanding of flash 
 +memory error patterns. To enable such understanding, we have designed and 
 +implemented a framework for fast and accurate characterization of flash 
 +memory throughout its lifetime. Using this hardware platform, we examine 
 +the complex flash errors that occur at 30-40nm flash technologies. We 
 +demonstrate distinct error patterns, such as cycle-dependency, 
 +locationdependency and value-dependency, for various types of flash 
 +operations. We analyze the discovered error patterns and explain why they 
 +exist from a circuit and device standpoint. Based on the error pattern, we 
 +propose flash correct and refresh (FCR) as an example that leverage the 
 +error patterns to improve flash endurance lifetime.
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=====Bio===== =====Bio=====
-Michael Papamichael received his MSc from the University of Crete and is currently a PhD student in the Computer Science Department at Carnegie Mellon University supported by an Intel Fellowship. His research interests are in the area of computer architecture, with emphasis on FPGA-based computing, uncore modeling and Networks-on-Chip.+Yu Cai is now a PhD candidate in ECE departemnt of Carnegie Mellon 
 +University advised by Prof. Ken Mai. His current interest includes error 
 +correction codes for NAND flash memory, FPGA hardware prototyping.
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