This shows you the differences between two versions of the page.

Link to this comparison view

seminars:seminar_12_11_27 [2012/11/25 13:20]
seminars:seminar_12_11_27 [2017/09/20 22:02] (current)
Line 1: Line 1:
 +======Error Patterns in MLC NAND Flash Memory: Measurement,​ Analysis and Application======
 +Tuesday Nov. 27, 2012\\
 +HH D-210\\
 +**Yu Cai (CMU)**\\
 +As NAND flash memory manufacturers scale down to smaller process
 +technology nodes and store more bits per cell, reliability and endurance
 +of flash memory reduce. Wear-leveling
 +and error correction coding can improve both reliability and endurance,
 +but finding effective algorithms requires a strong understanding of flash
 +memory error patterns. To enable such understanding,​ we have designed and
 +implemented a framework for fast and accurate characterization of flash
 +memory throughout its lifetime. Using this hardware platform, we examine
 +the complex flash errors that occur at 30-40nm flash technologies. We
 +demonstrate distinct error patterns, such as cycle-dependency,​
 +locationdependency and value-dependency,​ for various types of flash
 +operations. We analyze the discovered error patterns and explain why they
 +exist from a circuit and device standpoint. Based on the error pattern, we
 +propose flash correct and refresh (FCR) as an example that leverage the
 +error patterns to improve flash endurance lifetime.
 +Yu Cai is now a PhD candidate in ECE departemnt of Carnegie Mellon
 +University advised by Prof. Ken Mai. His current interest includes error
 +correction codes for NAND flash memory, FPGA hardware prototyping.
 +**[[seminars| Back to the seminar page]]**