Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes
Tuesday, Sept. 18
Hamerschlag Hall D-210
Where: Hamerschlag Hall D-210
Berkin Akin (CMU)
Prevailing VLSI trends point to a growing gap in the scaling of on-chip processing throughput and off-chip memory bandwidth. Therefore, increasingly, an efficient use of memory bandwidth must become a first-class design consideration in order to fully utilize the processing capability of highly concurrent processing platforms like FPGAs. In this talk, I present key aspects of this challenge in
developing FPGA-based implementations of two-dimensional fast Fourier transform (2D-FFT) where the large datasets must reside off-chip in DRAM. Our scalable implementations address the memory bandwidth bottleneck through both (1) algorithm design to enable efficient DRAM access patterns and (2) datapath design to extract the maximum compute throughput for a given level of memory bandwidth. The evaluations show that our FPGA-based implementations of 2D-FFT are more efficient than 2D-FFT running on state-of-the-art CPUs and GPUs in terms of the ratio between achieved performance and available memory bandwidth and in terms of the ratio between achieved performance and power dissipation.
Berkin Akin is a third year PhD student in Electrical and Computer Engineering Department. His research interests include FPGA-based computing, digital hardware design, DSP and computer architecture. He works closely with Professors James Hoe and Franz Franchetti. He received his B.S. in Electrical and Electronics Engineering from METU, Turkey in 2010.
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