Intelligent Cache Management for Reducing Memory System Waste

Thursday May 24, 2012
CIC 4th floor Panther Hollow
12:00 pm

Samira Khan (CS, UT San Antonio)


Improvements in CMOS process technology have resulted in faster processors in each generation for the last several decades. The current trend is to increase core count to achieve higher throughput. However, this focus limits the performance of single-threaded workloads. At the same time, power constraints are limiting the number of transistors that can be active at a given time. We can no longer rely on improvements in process technology to speed up the processors. Thus, processor performance largely depends on microarchitectural improvement providing higher efficiency.

In my work, I propose performance improvement by reducing inefficiencies in microarchitectural structures. Modern processor performance is quite sensitive to the last-level cache capacity and miss latency. My work reduces memory system waste while improving performance using the cache efficiently.


Samira Khan is a PhD candidate in the Department of Computer Science at the University of Texas at San Antonio. Her primary research interest lies in the general area of computer architecture, with particular emphasis on reducing inefficiencies of memory system in modern processors. She has earned her BS in Computer Science and Engineering from the Bangladesh University of Engineering and Technology (BUET).

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