Matching access and error patterns for low Vcc L1 cache architecture

Thursday Aug. 4, 2011
Hamerschlag Hall D-210
2:00 pm

Sungjoo Yoo


Large SRAMs are the practical bottleneck to achieving a low supply voltage because they suffer from process variation-induced bit errors at a low supply voltage. In this talk, we present an error-resilient cache architecture that resolves the drawbacks of previous approaches, the performance degradation at a low supply voltage caused by cache misses incurred by accesses to faulty resources. We utilize cache access locality and error-free resources in a cost-effective manner. We classify cache lines into fully accessed and partially accessed groups and apply appropriate methods to each group. For the partially accessed group, we propose a method of matching memory access behavior and error locations with intra-cache line word-level remapping. In order to reduce the area overhead used to store the cache access information history, we present an access pattern-learning line-fill buffer. For the fully accessed group, we propose utilizing error-free assist functions in the cache, i.e., a line-fill buffer and victim cache with no error at the target minimum supply voltage. We also present an error-aware prefetch method that allows us to utilize the error-free victim cache to achieve a further reduction in cache misses to faulty words. We present experimental results obtained with SPEC benchmarks and a Pin-based simulation environment.


Sungjoo Yoo is currently an assistant professor at Department of EE, POSTECH, Korea. He received Ph.D. from Seoul National Univ. in 2000. He worked as researcher at TIMA laboratory, Grenoble France from 2000 to 2004. He was also with Samsung System LSI from 2004 to 2008, where he led system-on-chip architecture design team and was involved in architecture designs for mobile application processors and solid state disk. His research interests include software, architecture and RTL design for low power SoC, and memory and storage hierarchy from cache, DRAM, phase-change RAM to solid state disk. He received Best Paper Award at International SoC Conference (ISOCC) in 2006 and Best Paper Award nominations at Design Automation Conference (DAC) in 2011 and Design Automation and Test in Europe (DATE) in 2002 and 2009.

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