Tuesday Apr. 27, 2010
Hamerschlag Hall D-210
The Ohio State University
Power management in chip multiprocessors continues to be one of the primary concerns for chip designers. One power management technique that is quickly gaining popularity is near-threshold operation. The technique consists of lowering the supply voltage of the entire chip or parts of the chip to a level that is very close to the threshold voltage. This significantly reduces current flow, resulting in dramatic reductions in power consumption (100X). These savings however, come at the cost of lower operating frequencies (10X) and orders of magnitude lower reliability. In near-threshold, SRAM structures such as caches experience bit failure rates that exceed 4%, rendering an unprotected memory virtually useless.
We propose a novel error correction technique based on turbo product codes that allows caches to continue to operate in near-threshold, with very low power consumption, while trading off some of the cache capacity to store parity protection information. Our implementation is flexible, allowing protection to be disabled in error-free high voltage operation and selectively enabled as the voltage is lowered and the error rate increases. It achieves significantly higher error correction compared to previous cache protection techniques, enabling up to 15X higher cache capacity at low voltages. When compared to a system that uses an unprotected cache in near threshold, the our system achieves a 40% reduction in the energy delay product.
Radu is an Assistant Professor in the Department of Computer Science and Engineering at Ohio State University. He received his PhD from University of Illinois at Urbana-Champaign. His research interests include computer architecture, nanoscale technology scaling, reliability, variability and power management, hardware support for software debugging. He was the recipient of the W. J. Poppelbaum award in 2008 from University of Illinois for his research in computer architecture.