Tuesday Jan. 26, 2010
Hamerschlag Hall B-206 (Note the change in location)
University of Pittsburgh
Technology scaling has led to the integration of many cores into a single chip. As a result, on-chip interconnection networks start to play a more and more important role in determining the performance and power of the entire chip. Packet-switched network-on-chip (NoC) has provided a scalable solution to the communications for tiled multicore processors. However the virtual-channel (VC) buffers in the NoC consume significant dynamic and leakage power of the system. To improve the energy efficiency of the router design, it is advantageous to use small buffer sizes while still maintaining throughput of the network.
We propose two new virtual channel allocation (VA) mechanisms, termed Fixed VC Assignment with Dynamic VC Allocation (FVADA) and Adjustable VC Assignment with Dynamic VC Allocation (AVADA). The idea is that VCs are assigned based on the designated output port of a packet to reduce the Head-of-Line (HoL) blocking. Also, the number of VCs allocated for each output port can be adjusted dynamically. Unlike previous buffer-pool based designs, we only use a small number of VCs to keep the arbitration latency low. Simulation results show that FVADA and AVADA can improve the network throughput by 41% on average, compared to a baseline design with the same buffer size. AVADA can still outperform the baseline even when our buffer size is halved. Moreover, we are able to achieve comparable or better throughput than a previous dynamic VC allocator while reducing its critical path delay by 60%. Our results prove that the proposed VA mechanisms are suitable for low-power, high-throughput, and high-frequency on-chip network designs.
Yi Xu is a PhD candidate in the Department of Electrical and Computer Engineering at the University of Pittsburgh. Her advisor is Professor Jun Yang and Professor Youtao Zhang. She received her B.S. and M.S. in Microelectronics from Nanjing University, China in 2004 and 2007, respectively. She is a student member of the IEEE. Her research interests include efficient interconnection architecture design for 2D/ 3D Chip Multi-Processor (CMP) and Network-on-Chip (NoC).