Core Fusion Revisited: Overcoming Single-Thread Performance Hurdles

Tuesday Oct. 6, 2009
Hamerschlag Hall D-210
4:00 pm

Janani Mukundan
Cornell University


Chip Multiprocessors (CMPs) represent an at-tractive approach for sustaining scalable performance improvement in the billion-transistor era. Although the prime target of CMPs is highly parallel codes, many of the software products being written are still single-threaded applications, and even many parallel codes still contain nontrivial sequential sections. This poses a difficult design trade-off for CMPs: On the one hand, CMPs designed for fine-grained parallelism are unable to match the performance of a monolithic wide-issue superscalar core on sequential codes. On the other hand, increasing the size of the cores in a CMP may come at the expense of sheer processor count, thereby hurting the scalability of parallel programs. Core Fusion has been proposed recently to gracefully accommodate software diversity. It is a reconfigurable CMP architecture where groups of fundamentally independent cores can dynamically “fuse” into larger, more aggressive processors. Al-though Core Fusion is capable of sustaining high performance for parallel applications, as well as en-hanced performance for sequential codes, in the latter case it still falls short of an area-equivalent monolithic out-of-order processor. In this talk, I will introduce two techniques to improve the performance of sequential applications on Core Fusion: (a) a retirement management unit that supports synchronized commit among distri-buted ROBs in a CMP, and (b) a new improved instruction steering algorithm that helps reduce performance losses due to cross-core operand communication. By incorporating these techniques to Core Fusion, we are able to come within 3.5% of the performance of an area equivalent wide-issue out-of-order processor.


Janani Mukundan is a third year PhD student in the ECE department at Cornell University. She completed her Master's degree in Computer Science from North Carolina State University in 2006. She researches the applicability and effectiveness of using machine learning to solve computer architecture problems. Janani is being advised by José Martínez at Cornell.

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