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seminars:seminar_05_09_14 [2017/09/21 02:02] (current) |
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+ | ======Title: How to feed data to your accelerator?====== | ||
+ | ==== Arrvindh Shriraman ==== | ||
+ | == Friday, May 9th, 11am == | ||
+ | == Panther Hollow, CIC == | ||
+ | ===Abstract:=== | ||
+ | To counter the loss of Dennard scaling chip designers have focused on energy-efficient compute accelerators. It imperative to improve the energy efficiency of data delivery while also ensuring that the memory model itself is comprehensible to a wide variety of programmers. | ||
+ | |||
+ | In this talk, I will focus on our recent IEEE MICRO TOP PICKs work on providing energy efficient cache coherence for accelerators. I will discuss a new time-based coherence framework, called Temporal Coherence (TC), that exploits globally synchronized counters in single-chip systems to develop a streamlined coherence protocol. I will present two memory models: TC-strong and TC-weak for accelerators, and evaluate the performance benefits of weak memory models . Finally, I will discuss important on-chip communication optimizations enabled by TC to reduce data transfer latency and NOC bandwidth. | ||
+ | |||
+ | ===Bio:=== | ||
+ | Arrvindh Shriraman is an assistant professor Simon Fraser University (Canada) where he co-leads the SYNAR research group. His research interests include multiprocessor system design, hardware-software interface, and parallel programming models. He received a PhD in computer science from the University of Rochester. |