Tuesday March 17, 2009
Hamerschlag Hall D-210
As industry rides the transistor density growth in multicore processors by providing more and more cores, these will exert increasing levels of pressure on shared system resources. Efficient resource management becomes critical to obtaining high utilization, and eliminating potential bandwidth, latency, and cost barriers in multicore systems. Unfortunately, current hardware policies for microarchitectural resource management are ad hoc at best, and are generally incapable of providing basic functionalities like anticipating the long-term consequences of scheduling decisions (planning), or generalizing from experience obtained through past resource allocation decisions to act successfully in new situations (learning). As a result, current hardware controllers tend to grossly underutilize the (already limited) platform resources available.
In this talk, using the problem of memory scheduling as context, I will advocate for the use of machine learning technology in designing self-optimizing, adaptive hardware capable of planning, learning, and continuously adapting to changing workload demands. A machine learning approach allows the hardware designer to focus on -what- performance target the hardware should accomplish, and -what- system variables might be useful to ultimately derive a good control policy, rather than devising a fixed policy that describes exactly -how- the hardware should accomplish that target. The result is higher-performing, more flexible hardware.
José Martínez (MS ’99, Ph.D ’02 UIUC) is associate professor of electrical and computer engineering, and graduate field member of computer science at Cornell. His research work has earned several awards; among them: two IEEE Micro Top Picks in Computer Architecture papers; a HPCA Best Paper Award; a NSF CAREER Award; and an IBM Faculty Award. He has been recognized with a 2005 Kenneth A. Goldman '71 Excellence in Teaching Award, and as a 2007 Merrill Presidential Teacher. A two-time recipient of the Spanish government's National Award for Academic Excellence, he held a four-year graduate fellowship from the Bank of Spain. While a graduate student at UIUC, he was inducted into the Honor Society of Phi Kappa Phi. He is a member of the Computer Systems Laboratory and the Intelligent Information Systems Institute at Cornell, as well as the ACM, the IEEE, and the SHPE societies.