With the global pool of data growing at 2.5 quintillion bytes per day and 90% of it produced in the last two years, there is no doubt the era of big data has arrived. This talk presents a targeted deployment of hardware accelerators to improve the throughput and energy efficiency of large-scale data processing. This talk describes Database Processing Units, or DPUs, a class domain-specific database processors that can efficiently handle database applications, and present the instruction set architecture, microarchitecture, and hardware implementation of one DPU, called the Q100. The Q100 has a collection of heterogeneous ASIC tiles that process relational tables and columns quickly and energy-efficiently. The architecture uses coarse grained instructions that manipulate streams of data, thereby maximizing pipeline and data parallelism, and minimizing the need to time multiplex the accelerator tiles and spill intermediate results to memory. This talk will outline the motivation, design, evaluation and challenges of such data processing systems.
Martha Kim is an Assistant Professor of Computer Science at Columbia University where she leads the ARCADE Lab. Kim's research interests are in computer architecture, parallel programming, compilers, and low-power computing. Her work has explored low-cost chip manufacturing systems, reconfigurable communication networks, and fine-grained parallel application profiling techniques. Her current research focuses on hardware and software techniques to improve the usability of hardware accelerators as well as data-centric accelerator design. Kim holds a PhD in Computer Science and Engineering from the University of Washington and a bachelors in Computer Science from Harvard University. She is the recipient of the 2013 Rodriguez Family Award in recognition of the research achievements of underrepresented junior faculty and a 2013 NSF CAREER award.