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Tuesday February 10, 2009
Hamerschlag Hall D-210
Carnegie Mellon University
Prior research demonstrates that temporal memory streaming and related address-correlating prefetchers improve performance of servers though increased memory level parallelism. Unfortunately, these prefetchers require large on-chip meta-data storage. In this talk, I will describe the requirements for storing predictor meta-data for temporal memory streaming in off-chip memory while still achieving 90% of the performance potential of idealized on-chip meta-data storage.
Mike is a fifth year PhD candidate in the Computer Architecture Laboratory at Carnegie Mellon, where he is advised by Prof. Babak Falsafi. Mike's research interests include processors and the software that runs on them. His work has primarily been devoted to finding ways to improve processor performance through hiding the latency of modern memory systems.