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seminars:a_runtime_framework_for_adaptive_realtime_streaming_applications_on_fpgas [2018/05/03 01:23] jiyuanz |
seminars:a_runtime_framework_for_adaptive_realtime_streaming_applications_on_fpgas [2018/05/03 01:24] jiyuanz |
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| - | =====Title:A Runtime Framework for Adaptive Realtime Streaming Applications on FPGAs===== | + | =====A Runtime Framework for Adaptive Realtime Streaming Applications on FPGAs===== |
| Wednesday March 21, 2018\\ | Wednesday March 21, 2018\\ | ||
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| Time: 4:30PM\\ | Time: 4:30PM\\ | ||
| - | Abstract: | + | =====Abstract===== |
| Field Programmable Gate Arrays (FPGAs) have been undergoing a dramatic transformation from a logic to a computing technology. Despite the phenomenally rapid progress we have seen in the last few years, there is still much untapped opportunities in FPGAs’ full computing potential. FPGA is a programmable device like processors but has been traditionally used as an ASIC substitute. For over a decade, dynamic partial reconfiguration (DPR) has made it possible to reconfigure a region of the FPGA fabric while the remainder of the fabric continue to operate uninterrupted. However, DPR has seen very little use in FPGAs’ traditional ASIC-substitute roles. In order to exploit FPGA full dynamic programmability potential, frameworks to manage FPGA resources dynamically and efficiently are needed. | Field Programmable Gate Arrays (FPGAs) have been undergoing a dramatic transformation from a logic to a computing technology. Despite the phenomenally rapid progress we have seen in the last few years, there is still much untapped opportunities in FPGAs’ full computing potential. FPGA is a programmable device like processors but has been traditionally used as an ASIC substitute. For over a decade, dynamic partial reconfiguration (DPR) has made it possible to reconfigure a region of the FPGA fabric while the remainder of the fabric continue to operate uninterrupted. However, DPR has seen very little use in FPGAs’ traditional ASIC-substitute roles. In order to exploit FPGA full dynamic programmability potential, frameworks to manage FPGA resources dynamically and efficiently are needed. | ||
| In this talk, I will present my ongoing work which investigates the necessary mechanisms and policies (hardware and software) to realize such a runtime framework for executing adaptive realtime streaming applications using DPR. Notably, I will present major challenges when using DPR, as well as some novel techniques to help overcome those challenges. The runtime framework supports multiple dependent and independent tasks that dynamically share an FPGA’s logic fabric both spatially and temporally (time-sharing) . | In this talk, I will present my ongoing work which investigates the necessary mechanisms and policies (hardware and software) to realize such a runtime framework for executing adaptive realtime streaming applications using DPR. Notably, I will present major challenges when using DPR, as well as some novel techniques to help overcome those challenges. The runtime framework supports multiple dependent and independent tasks that dynamically share an FPGA’s logic fabric both spatially and temporally (time-sharing) . | ||
| - | Bio: | + | =====Bio===== |
| Marie Nguyen is a Ph.D. candidate in the Electrical and Computer Engineering department at CMU. Her research interests include computer architecture, hardware acceleration and computer vision. She is also particularly interested in designing runtime systems for FPGAs. | Marie Nguyen is a Ph.D. candidate in the Electrical and Computer Engineering department at CMU. Her research interests include computer architecture, hardware acceleration and computer vision. She is also particularly interested in designing runtime systems for FPGAs. | ||
