The CALCM reading group meets weekly to discuss papers from recent Computer Architecture conferences. Interested students should sign up for specific papers that they would be interested in leading.
Role of group leaders:
- Introducing the paper (the problem/motivation, basic ideas of the solution, and a very brief overview of results, strengths, weaknesses)
- Raising questions related to the paper and the problem at hand
- Identifying some more blue-sky brainstorming topics related to the problem at hand
The leader's job is not to lecture about the paper for an hour, but simply to introduce the paper (in 5-10 minutes) and then lead the discussion, if needed.
Every Wednesday in HH-1205, 5-6pm
If you have general questions/concerns, please contact the reading group organizers: Michael Papamichael (papamix AT cs.cmu.edu), Eric Chung (firstname.lastname@example.org).
If you are having trouble with login/editing the wiki, please contact Michael Papamichael (papamix AT cs.cmu.edu).
- If you wish to present a paper you need to edit this wiki page and:
- Add the paper in the schedule further below
- Remove the paper from the list of papers.
- To add presentation slides edit the wiki and click on the “Add Images and other files” button (it looks like a picture frame). Make sure the uploaded ppt file name matches the place-holder name in the schedule.
- To add/edit discussion notes just click on the “Notes” link in the schedule and edit the corresponding wiki page.
- Operating System Support for Overlapping-ISA Heterogeneous Multi-Core Architectures
- Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing
- Boosting Single-thread Performance in Multi-core Systems through Fine-grain Multi-Threading
- Simultaneous Speculative Threading: A Novel Pipeline Architecture for Chip Multiprocessors
- Architecting Phase Change Memory as a Scalable DRAM Alternative TOGETHER WITH
Scalable High Performance Main Memory System Using Phase-Change Memory Technology
- Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance
- End-to-End Register Data-Flow Continuous Self-Test
- Online Design Bug Detection: RTL-Level Analysis, Flexible Mechanisms, and Evaluation
- A Performance-Correctness Explicitly-Decoupled Architecture
- Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach
- A Low-Radix and Low-Diameter 3D Interconnection Network Design
- BlueShift: Designing Processors for Timing Speculation from the Ground Up
- Anomaly-Based Bug Prediction, Isolation, and Validation: An Automated Approach for Software Debugging
- DRAM errors in the wild: A Large-Scale Field Study
|Sep 20||Cohesion: A Hybrid Memory Model for Accelerators||Marek T.||Slides|
|Oct 4||Forwardflow: A scalable core for power-constrained CMPs||Chris F.||Slides|
|Oct 18||The ZCache: Decoupling Ways and Associativity||Vivek S.|
|Nov 1||Composing Parallel Software Efficiently with Lithe||Yoongu K.|
|Nov 15||TBD||Evangelos V.|
others: Rachael, Rachata
- A mailing list keeps members informed of seminars and events related to CALCM. Subscribe here.
- Recommended readings:
- Mark Hill, Oral Presentation Advice
- Alan Jay Smith, The Task of the Referee, IEEE Computer, Apr. 1990