Scaling the Bandwidth Wall: Challenges in and Avenues for CMP Scaling

  • Can you change SW to lower alpha value. (alpha –> cache size dependency of workload)
  • Evangelos: What happens when power comes into question? Nikos: Leakage of caches causes significant power consumption.
  • Discussion about stacked layers: layering causes an increase of about 10 degrees Celcius, which translates to 30W (Nikos)
  • Nikos disagrees with Data sharing argument in paper. Nikos: contrary to what paper claims data sharing decreases the amount of required cache as the number of cores. When they examine data sharing it's not clear if looking at the number of evicted cache lines that are shared gives an accurate number of shared data.
  • Nikos: It would be nice if they looked at power/frequency constraints and also examined stacking of DRAM memory (instead of only considering 3D DRAM caching). This would probably completely solve the bandwidth problem. DRAM has a power consumption of about 4-5W/GB. For stacked DRAM access time is about 11ns!