Claytronics (Programmable Matter)

ENYAC (Energy Aware Architecture)

Power dissipation has become a critical design concern in recent years, driven by the increased levels of complexity and emergence of mobile applications. Our research addresses this problem by providing architectural and software solutions for reducing the energy requirements of general purpose or embedded applications. Since what drives the power consumption of modern processors is the actual software that runs on it, our research also targets techniques for generating energy aware software and microarchitectural mechanisms to support it. www

Phoenix (C-to-HW Compile)

The Phoenix project explores the direct implementation of programs in (reconfigurable) hardware. The benefits of this approach are: low energy consumption, reduced design and manufacturing costs, high performance. www


CMU's Impetus group focuses on the design, evaluation, and implementation of computer systems with emphasis on processor and memory architecture. www

LBA (Log-based Architecture)

ProtoFlex (FPGA Accelerated Simulation)

SimFlex (Full System Simulation)

Computer architects have long relied on software simulation to measure dynamic performance metrics (e.g. CPI) of a proposed design. Unfortunately, with the ever-growing size and complexity of modern microprocessors, detailed software simulators have become four or more orders of magnitude slower than their hardware counterparts. The low simulation throughput is especially prohibitive for large-scale multiprocessor systems because the simulation turnaround for these systems grows at least linearly with the number of processors.

This project proposes the SimFlex framework to support fast, accurate and flexible simulation of large-scale systems. SimFlex applies rigorous statistical sampling theory to reduce simulation turnaround by several orders of magnitude, while achieving high accuracy and confidence in estimates. SimFlex relies heavily on well-defined component interface models to facilitate both model integration and compile-time simultaor optimization. www

SPIRAL (DSP HW and SW generation)

The goal of SPIRAL is to push the limits of automation in software and hardware development and optimization for digital signal processing (DSP) algorithms and other numerical kernels beyond what is possible with current tools. The idea is to build intelligent code generators that, for a given problem like FFT, autonomously explore algorithmic choices and optimize at different levels of abstractions to find the best match to a given architecture or constraints. www

STeMS (Memory Streaming)

Technological advancements in semiconductor fabrication have led to an abundance of on-chip transistors, faster clock speeds, and unprecedented processor performance. In contrast, while DRAM capacity has increased commensurately, DRAM speeds have primarily lagged behind resulting in an ever-increasing processor/memory performance gap.

Spatio-Temporal Memory Streaming (STeMS) is a new memory system architecture in which memory moves in correlated groups (called spatio-temporal streams) rather than individual cache blocks to enhance fetch lookahead and memory-level parallelism, hide memory latency, and improve on-chip storage utilization and pin bandwidth. www

TRUSS (Fault-Tolerant Computing)

Server availability and reliability is now ever more a critical aspect of computing, because information processing and storage are becoming a key pillar of a modern society’s infrastruscture. Unfortunately, while availability and reliability are becoming increasing crucial, it is also ever more challenging to design, manufacture, and market reliable server platforms.

This project proposes the Total Reliability Using Scalable Server (TRUSS) architecture, a reliable, available, and servicable (RAS) hardware platform. TRUSS offers both cost and performance scalability unparalleled by conventional RAS-oriented servers by using commodity blade components interconnected through a scalable network and hardware distributed shared memory (DSM). www

Past Projects

Aura Pervasive Computing Project

Aura's goal is to provide each user with an invisible halo of computing and information services that persists regardless of location. Meeting this goal will require effort at every level: from the hardware and network layers, through the operating system and middleware, to the user interface and applications. www


Carnegie Mellon's Reconfigurable Computer Project addresses the two most significant problems with current reconfigurable computing systems: (1) traditional FPGAs have hard resource constraints, which makes it difficult for a compilation tool to consistently and easily generate applications, and (2) there is no mechanism to provide forward-compatibility, causing the investment in generating applications to be lost for future generations of silicon. www


The unabated growth in the number of transistors is resulting in a proportional increase in the chip's power dissipation. The PowerTap project proposes and investigates power-aware architectures in which software/hardware minimize power dissipation while maintaining high performance. The key observation behind our designs is that the demand for hardware resources widely varies both within and across applications. Our systems use mechanisms to dynamically identify and enable an application's required processor/memory resources, thereby eliminating power dissipation in unused resources.www


The goal of the Profet project is to avoid wasting time whenever we access data. To accomplish this, we proactively manage caches such that the data that you want is available in the cache before you actually need it.

The name “Profet” comes from “PROactive FETching data”. Profet is also a deliberate misspelling of both “prophet” (as in predicting the future, which is what we do improve cache performance) and “profit” (as in optimizing “cash” - sic), and it is pronounced like both of those words. www


The STAMPede project is investigating the architectural, compiler, and OS support necessary to effectively exploit single-chip multiprocessors. “STAMPede” stands for “Single-chip, Tightly-coupled Architecture for MultiProcessing.” www