Value prediction (VP) was proposed to enhance the performance of superscalar processors by breaking RAW dependencies. However, it has generally been considered too complex to implement. During this presentation, we will review different sources of additional complexity and propose solutions to address them.
First, existing context-based predictors may not be easily implemented. To that extent, we propose a new predictor, VTAGE, that does not suffer from the same shortcomings.
Second, we will focus on the complexity introduced by VP in the OoO engine: 1) Validation & recovery 2) Additional ports in the register file. We remark that predictions can be validated at retirement as long as very high prediction accuracy is enforced. We also argue that with VP, many instructions can be executed in-order in the front-end (predicted operands) or at retirement (predicted result). Thus, the OoO engine can be simplified.
Finally, we will dive into more technical considerations on the predictor infrastructure: providing multiple predictions per cycle, and reducing the predictor footprint.
Arthur Perais is a 3rd Ph.D. student with the Amdahl's Law is Forever (ALF) research team at INRIA Bretagne Atlantique (Rennes, France). He is advised by André Seznec. His research focuses on core microarchitecture and in particular, how to increase sequential performance. To do so, he is revisiting a speculation technique that was introduced in the mid 90's: Value Prediction. He is currently visiting Prof. Onur Mutlu's group and will be here until mid-April.