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		+	===== Archived CARL 2013 Contents =====
		+	===== The Third Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013), Davis, California - Saturday, December 7, 2013, Co-located with MICRO-46 ======
		+
		+	The Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL) is a new forum for presenting FPGA and reconfigurable logic research relevant to a computer architecture audience. In recent years, there has been a renewed interest in reconfigurable computing, driven by the need for greater computing performance and, at the same time, better power and energy efficiency. Reconfigurable computing is a key technology candidate to efficiently leverage exponential device scaling beyond current multicore processors.
		+
		+	This full-day workshop will be held on Saturday, December 7, 2013, co-located with MICRO-46 in Davis, CA.
		+
		+
		+	====== Program ======
		+
		+	Two categories of submissions were solicited for review, (1) new unpublished manuscripts and (2) audience-appropriate revisions of papers already published or under review outside of traditional computer architecture forums. (See [[:Home#Call_For_Papers|Call for Papers]] below.) Each 4~6-page submission was assigned to 4~5 members of the program committee for review. (Submissions selected for presentation at CARL are not published.)
		+	In addition, the program include a keynote presentation by Peter Hofstee (IBM Austin Research) and an invited talk by Zhiru Zhang (Cornell).
		+
		+	The final program include also invited talks.
		+
		+	* 8:00~8:50 **Breakfast**
		+	* 8:50~9:00 **Welcome**
		+	* 9:00~10:30 **Heterogeneous Computing** (Chaired by Derek Chiou, UT Austin/Microsoft)
		+	* **Keynote: Coherent shared memory reconfigurable acceleration on Power 7 and Power 8**, Peter Hofstee, IBM Austin Research Laboratory.
		+	* **A Model of Computation and Compiler for Heterogeneous Systems**, Kermin Fleming** * **, Intel Corporation; Joel Emer, Intel/MIT; Michael Adler, Intel Corporation. ({{carl2013_Fleming.pdf|PDF}})
		+	* 10:30~11:00 **Morning Break**
		+	* 11:00~12:30 **Infrastructure and Environments** (Chaired by Kees Vissers, Xilinx)
		+	* **PyCoRAM: Yet Another Implementation of CoRAM Memory Architecture for Modern FPGA-based Computing**, Shinya Takamaeda-Yamazaki** * **, Tokyo Institute of Technology; Kenji Kise, Tokyo Institute of Technology; James Hoe, Carnegie Mellon University. ({{carl2013_Takamaeda-Yamazaki.pdf|PDF}} | {{carl2013_Takamaeda_slides.pdf|slides}})
		+	* **A High-Performance Oblivious RAM Controller on the Convey HC-2ex Heterogeneous Computing Platform**, Martin Maas** * **, UC Berkeley; Eric Love, UC Berkeley; Emil Stefanov, UC Berkeley; Mohit Tiwari, UT Austin; Elaine Shi, University of Maryland, College Park; Krste Asanovic, UC Berkeley; John Kubiatowicz, UC Berkeley; Dawn Song, UC Berkeley. ({{carl2013_Maas.pdf|PDF}} | [[http://www.cs.berkeley.edu/~maas/slides/carl13-maas-talk.pdf |slides]])
		+	* **Augmenting FPGAs with Embedded Networks-on-Chip**, Mohamed Abdelfattah** * **, University of Toronto; Vaughn Betz, University of Toronto. ({{carl2013_Abdelfattah.pdf|PDF}} | [[http://www.eecg.utoronto.ca/~mohamed/carl13_pres.ppsx |slides]])
		+	* 12:30-1:30 **Lunch**
		+	* 1:30~3:00 **High-level Design and Synthesis** (Chaired by Carl Ebeling, Altera)
		+	* **Invited Talk: High-level synthesis for FPGAs: from prototyping to deployment**, Zhiru Zhang, Cornell University.
		+	* **GraphGen for CoRAM: Graph Computation on FPGAs**, Gabriel Weisz** * **, Carnegie Mellon University; Eriko Nurvitadhi, Intel Corporation; James Hoe, Carnegie Mellon University. ({{carl2013_Weisz.pdf|PDF}}|{{carl2013_Weisz_slides.pdf|slides}})
		+	* 3:00~3:30 **Afternoon Break**
		+	* 3:30~4:30 **Prototyping and Simulation** (Chaired by David Penry, Brigham Young University)
		+	* **HySIM: Towards a Scalable, Accurate and Fast Simulator for Manycore Processors**, Kramer Straube** * **, UC Davis; Huan Zhang, UC Davis; Christopher Nitta, UC Davis; Matthew Farrens, UC Davis; Venkatesh Akella, UC Davis. ({{carl2013_Straube.pdf|PDF}} | {{carl2013_straube_slides.pdf |slides}})
		+	* **FPGA Prototyping of Manycore Multinode Systems for Irregular Applications**, Marco Ceriani, Politecnico di Milano; Simone Secchi, Università di Cagliari; Antonino Tumeo** * **, PNNL; Oreste Villa, NVIDIA; Gianluca Palermo, Politecnico di Milano. ({{carl2013_Tumeo.pdf|PDF}} | {{carl2013_Tumeo_slides.pdf|slides}})
		+	* 4:30~4:45 **Closing**
		+
		+	======Call for Papers======
		+
		+	**Research Papers.** We invite research papers from all areas of FPGA and reconfigurable logic that impact the computer architecture community.  Major areas of interests include, but are not limited to:
		+
		+	* New FPGA architectures and reconfigurable fabric designed to support computing
		+	* Heterogeneous computing processors and systems that incorporate reconfigurable logic
		+	* Computation models and programming tools for reconfigurable and heterogeneous computing
		+	* State-of-the-art (ready-for-use) reconfigurable computing platforms and infrastructure
		+	* Algorithms and applications for reconfigurable computing (including FPGA-based prototyping and simulation of computer systems)
		+	* Evaluations of reconfigurable computing in terms of performance, power/energy, flexibility and cost, especially in comparison to other hardware paradigms (multicore, GPU, ASICs, etc.).
		+
		+	We will accept submissions in two categories:  (1) new unpublished manuscripts (okay if under review by a conference of a later date), and (2) audience-appropriate revisions of papers already published outside of traditional computer architecture forums (ISCA, MICRO, HPCA, PACT, etc.).  Papers selected for presentations will not be published in any formal proceedings.
		+
		+	A submission should be 4~6 pages in double-column format.  The review process is not blind; please include authors' names and affiliations.  Please clearly indicate whether a submission is category 1 or 2 in the header area of the submission.  If category 2, the source materials must be explicitly introduced in both the abstract and introduction.
		+
		+	**Questions?** Please email questions about this Call-for-Papers to jhoe@ece.cmu.edu.
		+
		+	====== Submission Site ======
		+
		+	Please submit your paper through the [[https://cmt.research.microsoft.com/CARL2013/|submission site]] before October 7, 2013. (We like to thank Microsoft Research for this service.)  If you encounter any problems with your submission, please email jhoe@ece.cmu.edu.
		+
		+	====== Important Dates ======
		+
		+	* **Submission Deadline:** October 7, 2013 \\
		+	* **Notification of Selection:** November 4, 2013 \\
		+	* **Final Paper Submission:** November 25, 2013 \\
		+	* **Workshop:** December 7, 2013\\
		+
		+	====== Technical Program Committee ======
		+
		+	* Vaughn Betz, University of Toronto
		+	* Doug Burger, Microsoft Research
		+	* Eric Chung, Microsoft Research
		+	* Srini Devadas, MIT
		+	* Carl Ebeling, Altera
		+	* Shih-Lien Lu, Intel
		+	* Robert Mullins, University of Cambridge
		+	* David Penry, Brigham Young University
		+	* Vijay Reddi, University of Texas, Austin
		+	* Graham Schelle, Xilinx
		+	* Sunil Shukla, IBM
		+	* Satnam Singh, Google
		+	* Chuck Thacker, Microsoft Research
		+	* Kees Vissers, Xilinx
		+	* Tao Wang, Peking University
		+	* John Wawrzynek, UC Berkeley
		+
		+	====== Organizers ======
		+
		+	* [[http://users.ece.utexas.edu/~derek/|Derek Chiou]], UT Austin/Microsoft\\
		+	* [[http://www.intel.com/pressroom/kits/bios/jemer.htm | Joel Emer]], Intel/MIT\\
		+	* [[http://www.ece.cmu.edu/~jhoe|James C. Hoe]], CMU \\