The Third Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2013)

Davis, California - Saturday, December 7, 2013

Co-located with MICRO-46

http://www.ece.cmu.edu/calcm/carl

---------------

LOOK FOR US NEXT TIME WITH ISCA 2015!!

Archived CARL 2010 Contents

The First Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2010), Atlanta, Georgia - Sunday, December 5, 2010, Co-located with MICRO-43

The Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL) is a new forum for presenting FPGA and reconfigurable logic research relevant to a computer architecture audience. In recent years, there has been a renewed interest in reconfigurable computing, driven by the need for greater computing performance and, at the same time, better power and energy efficiency. Reconfigurable computing is a key technology candidate to efficiently leverage exponential device scaling beyond current multicore processors.

This full-day workshop will be held on Sunday, December 5, 2010, co-located with MICRO-43 in Atlanta, George. The meeting will include keynote presentations, research presentations and a brainstorming panel.

Program of Invited Presentations

Two categories of submissions were solicited for review, (1) new unpublished manuscripts and (2) audience-appropriate revisions of papers already published or under review outside of traditional computer architecture forums. (See Call for Papers below.) Each 4~6-page submission was assigned to 4 members of the program committee for review. At the end, the program committee invited 9 out of the 20 submitted papers for presentation at the CARL Workshop. Submissions selected for presentation at CARL are not published.

The workshop will be held on Sunday, December 5th in Room 1456, Klaus Advanced Computing Building, Georgia Tech.

  • 8:45-10:00 Keynote
    • Welcome, Derek Chiou, Joel Emer and James C. Hoe
    • Co-Designing a COTS Re-configurable Exascale Computer, Steven J. Wallach (Convey Computer) (PDF)
  • 10:00-10:30 Coffee break
  • 10:30-12:00 Computing Abstractions (Kees Vissers, Xilinx)
    • Rethinking FPGA Computing with a Many-Core Approach, John Wawrzynek (UCB); Mingjie Lin (UCB); Ilia Lebedev (UCB); Shaoyi Cheng (UCB); Daniel Burke (UCB) (PDF)
    • A Model for Programming Large-Scale Configurable Computing Applications, Carl Ebeling (University of Washington); Scott Hauck (University of Washington); Corey Olson (University of Washington); Maria Kim (University of Washington); Cooper Clausen (University of Washington); Boris Kogon (University of Washington) (PDF)
    • CoRAM: An In-Fabric Memory Abstraction for FPGA-based Computing, Eric Chung (Carnegie Mellon University); James Hoe (Carnegie Mellon University); Ken Mai (Carnegie Mellon University) (PDF)
  • 12:00-1:30 Lunch
  • 1:30-3:00 Languages and Environments (Graham Schelle, Intel)
    • LEAP: A Virtual Platform Architecture for FPGAs, Angshuman Parashar (Intel); Michael Adler (Intel); Kermin Fleming (MIT); Michael Pellauer (MIT); Joel Emer (Intel/MIT) (PDF, webpage)
    • Programming the Convey HC-1 with ROCCC 2.0, Jason Villarreal (Jacquard Computing, Inc); Adrian Park (Jacquard Computing Inc.); Roby Atadero (Jacquard Computing Inc.); Walid Najjar (University of California, Riverside); Glen Edwards (Convey Computers) (PDF, webpage)
    • A Methodology for Leveraging Reconfigurability in Domain Specific Languages, Maysam Lavasani (UT Austin); Larry Dennison (Lightwolf Tech); Derek Chiou (UT Austin) (PDF)
  • 3:00-3:30 Coffee break
  • 3:30-5:00 Computing and Simulation (Sunil Shukla, IBM)
    • An Architecture & Mechanism for Supporting Speculative Execution of a Context-full Reconfigurable Function Unit, Tao Wang (Intel); Zhihong Yu (Intel); Peng Li (Intel); Yuan Liu (Intel); Dong Liu (Intel); Joel Emer (Intel/MIT) (PDF)
    • HLS^2 : High-Level Synthesis for High-Level Simulation using FPGAs, Varun Koyyalagunta (UT-Austin); Hari Angepat (UT Austin); Derek Chiou (UT Austin) (PDF)
    • SPICE2: Spatial Processors Interconnected for Concurrent Execution for accelerating the SPICE Circuit Simulator using an FPGA, Nachiket Kapre (Caltech); Andre DeHon (U Penn) (PDF)
  • 5:00 Conclude

Call for Papers

We invite research papers from all areas of FPGA and reconfigurable logic that impact the computer architecture community. Major areas of interests include, but are not limited to:

  • New FPGA architectures and reconfigurable fabric designed to support computing
  • Heterogeneous computing processors and systems that incorporate reconfigurable logic
  • Computation models and programming tools for reconfigurable and heterogeneous computing
  • State-of-the-art (ready-for-use) reconfigurable computing platforms and infrastructure
  • Algorithms and applications for reconfigurable computing (including FPGA-based prototyping and simulation of computer systems)
  • Evaluations of reconfigurable computing in terms of performance, power/energy, flexibility and cost, especially in comparison to other hardware paradigms (multicore, GPU, ASICs, etc.).

We will accept submissions in two categories: (1) new unpublished manuscripts, and (2) audience-appropriate revisions of papers already published or under review outside of traditional computer architecture forums. Papers invited for presentations will not be published in any formal proceedings.

A submission should be 4~6 pages in double-column format. The review process is not blind; please include authors' names and affiliations. Please clearly indicate whether a submission is category 1 or 2. If category 2, the source materials must be clearly identified in the abstract and introduction.

Please email questions to jhoe@ece.cmu.edu.

(Download the CFP in PDF)

Submission Site

Please submit your paper through the submission site before October 1, 2010. (We like to thank Microsoft Research for this service.) If you encounter any problems with your submission, please email jhoe@ece.cmu.edu.

Important Dates

  • Submission Deadline: October 1, 2010
  • Notification of Selection: November 1, 2010
  • Final Paper Submission: November 22, 2010
  • Workshop: December 5, 2010

Technical Program Committee

  • Dave Albonesi, Cornell University
  • Derek Chiou, UT Austin
  • John Davis, Microsoft Research
  • Srini Devadas, MIT
  • Joel Emer, Intel/MIT
  • James Hoe, CMU
  • Shih-Lien Lu, Intel
  • Robert Mullins, University of Cambridge
  • David Penry, Brigham Young University
  • Graham Schelle, Intel
  • Sunil Shukla, IBM
  • Satnam Singh, Microsoft Research
  • Chuck Thacker, Microsoft Research
  • Kees Vissers, Xilinx
  • John Wawrzynek, UC Berkeley

Organizers

The CARL Logo is the creation of Sunil Shukla, IBM.