The Fourth Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2015)

Portland, Oregon - Sunday, June 14, 2015

Oregon Convention Center, Room D-132

Co-located with ISCA 2015

http://www.ece.cmu.edu/calcm/carl

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CARL 2015 Speaker: Eric S. Chung, Microsoft Research NExT

Accelerating Deep Convolutional Neural Networks Using Specialized Hardware in the Datacenter

Text analytics is the process of extracting information from large-scale unstructured text data and has various applications in business analytics, healthcare, and security domains. The size of the data sets is constantly growing in these domains, and extracting, in real time and at high speeds, patterns, correlations, and insights hidden in these data sets has significant value. To address the associated performance and energy-efficiency challenges and to exploit the data-access bandwidth more efficiently, we use hardware accelerators realized on field programmable gate arrays (FPGAs). A key component of our approach is a compiler that automatically transforms high-level text analytics queries into FPGA-optimized data flow pipelines. Our accelerators execute complex rule-based text analytics queries, consisting of hundreds of text-processing functions, an order of magnitude faster than the multi-threaded software implementations running on powerful multi-core processors.

Speaker Bio

Eric S. Chung is a Researcher in Microsoft Research NExT. His research focuses on the intersection of computer architecture and reconfigurable computing with FPGAs, and exploring disruptive uses of specialized hardware in high valued applications such as machine learning. He is a principal developer and contributor to the Catapult project at Microsoft, which uses a fabric of FPGAs to accelerate cloud services at scale in the datacenter. Eric received his PhD in electrical and computer engineering from Carnegie Mellon University and a BS in EECS from UC Berkeley.