The Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL) is a new forum for presenting FPGA and reconfigurable logic research relevant to a computer architecture audience. In recent years, there has been a renewed interest in reconfigurable computing, driven by the need for greater computing performance and, at the same time, better power and energy efficiency. Reconfigurable computing is a key technology candidate to efficiently leverage exponential device scaling beyond current multicore processors.
This full-day workshop will be held on Saturday, December 7, 2013, co-located with MICRO-46 in Davis, CA.
Two categories of submissions were solicited for review, (1) new unpublished manuscripts and (2) audience-appropriate revisions of papers already published or under review outside of traditional computer architecture forums. (See Call for Papers below.) Each 4~6-page submission was assigned to 4~5 members of the program committee for review. (Submissions selected for presentation at CARL are not published.)
In addition, the program include a keynote presentation by Peter Hofstee (IBM Austin Research) and an invited talk by Zhiru Zhang (Cornell).
The final program include also invited talks.
8:00~8:50 Breakfast
8:50~9:00 Welcome
9:00~10:30 Heterogeneous Computing (Chaired by Derek Chiou, UT Austin/Microsoft)
10:30~11:00 Morning Break
11:00~12:30 Infrastructure and Environments (Chaired by Kees Vissers, Xilinx)
PyCoRAM: Yet Another Implementation of CoRAM Memory Architecture for Modern FPGA-based Computing, Shinya Takamaeda-Yamazaki
* , Tokyo Institute of Technology; Kenji Kise, Tokyo Institute of Technology; James Hoe, Carnegie Mellon University. (
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slides)
A High-Performance Oblivious RAM Controller on the Convey HC-2ex Heterogeneous Computing Platform, Martin Maas
* , UC Berkeley; Eric Love, UC Berkeley; Emil Stefanov, UC Berkeley; Mohit Tiwari, UT Austin; Elaine Shi, University of Maryland, College Park; Krste Asanovic, UC Berkeley; John Kubiatowicz, UC Berkeley; Dawn Song, UC Berkeley. (
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slides)
Augmenting FPGAs with Embedded Networks-on-Chip, Mohamed Abdelfattah
* , University of Toronto; Vaughn Betz, University of Toronto. (
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slides)
12:30-1:30 Lunch
1:30~3:00 High-level Design and Synthesis (Chaired by Carl Ebeling, Altera)
3:00~3:30 Afternoon Break
3:30~4:30 Prototyping and Simulation (Chaired by David Penry, Brigham Young University)
HySIM: Towards a Scalable, Accurate and Fast Simulator for Manycore Processors, Kramer Straube
* , UC Davis; Huan Zhang, UC Davis; Christopher Nitta, UC Davis; Matthew Farrens, UC Davis; Venkatesh Akella, UC Davis. (
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slides)
FPGA Prototyping of Manycore Multinode Systems for Irregular Applications, Marco Ceriani, Politecnico di Milano; Simone Secchi, Università di Cagliari; Antonino Tumeo
* , PNNL; Oreste Villa, NVIDIA; Gianluca Palermo, Politecnico di Milano. (
PDF |
slides)
4:30~4:45 Closing
Research Papers. We invite research papers from all areas of FPGA and reconfigurable logic that impact the computer architecture community. Major areas of interests include, but are not limited to:
New FPGA architectures and reconfigurable fabric designed to support computing
Heterogeneous computing processors and systems that incorporate reconfigurable logic
Computation models and programming tools for reconfigurable and heterogeneous computing
State-of-the-art (ready-for-use) reconfigurable computing platforms and infrastructure
Algorithms and applications for reconfigurable computing (including FPGA-based prototyping and simulation of computer systems)
Evaluations of reconfigurable computing in terms of performance, power/energy, flexibility and cost, especially in comparison to other hardware paradigms (multicore, GPU, ASICs, etc.).
We will accept submissions in two categories: (1) new unpublished manuscripts (okay if under review by a conference of a later date), and (2) audience-appropriate revisions of papers already published outside of traditional computer architecture forums (ISCA, MICRO, HPCA, PACT, etc.). Papers selected for presentations will not be published in any formal proceedings.
A submission should be 4~6 pages in double-column format. The review process is not blind; please include authors' names and affiliations. Please clearly indicate whether a submission is category 1 or 2 in the header area of the submission. If category 2, the source materials must be explicitly introduced in both the abstract and introduction.
Questions? Please email questions about this Call-for-Papers to jhoe@ece.cmu.edu.
Please submit your paper through the submission site before October 7, 2013. (We like to thank Microsoft Research for this service.) If you encounter any problems with your submission, please email jhoe@ece.cmu.edu.
Submission Deadline: October 7, 2013
Notification of Selection: November 4, 2013
Final Paper Submission: November 25, 2013
Workshop: December 7, 2013
Vaughn Betz, University of Toronto
Doug Burger, Microsoft Research
Eric Chung, Microsoft Research
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Carl Ebeling, Altera
Shih-Lien Lu, Intel
Robert Mullins, University of Cambridge
David Penry, Brigham Young University
Vijay Reddi, University of Texas, Austin
Graham Schelle, Xilinx
Sunil Shukla, IBM
Satnam Singh, Google
Chuck Thacker, Microsoft Research
Kees Vissers, Xilinx
Tao Wang, Peking University
John Wawrzynek, UC Berkeley