Half Day Workshop
Sunday, March 14 - PM slot
Organizers: Shih-Lien Lu (firstname.lastname@example.org), Bruce Jacob (U of Maryland), John Carter (University of Utah)
Description: WAMT is a half-day workshop that provides a forum for researchers and practitioners from academia and industry to discuss advances in how emerging new memory technologies may impact the memory hierarchy. We are on the cusp of another dramatic shift in the memory system driven by emerging technology trends and the performance miss match of memory and CPU.
On the technology side, for example, eDRAM (DRAM embedded on the CPU die or in the same package) offers the potential to integrate large amount of memory (e.g. IBM’s Power7 has 32MB of eDRAM) with today’s CPUs at near-cache-access speeds. Device scaling will increase the eDRAM size to 128MB in 4 years and to 1GB in 10 years. At the same time, another fast growing technology trend involves the integration of flash in the platform. Although large hard disk drives (HDD) are much cheaper bit for bit than large solid state disks (SSD), this doesn’t apply for smaller disks. Today, an 8GB HDD costs roughly the same as an 8GB SSD. In 4 years, this number will increase to 32GB, and in 10 years it will increase to 1TB. Besides the above two current employed technologies, several other new memory devices are gaining rapid attention such as Phase Change Memory (PCM) and Spin-Torque Transfer Magnetic RAM (STT MRAM). Of course there is also the capability to stack die or wafer of both new memory technologies as well as the traditional work horse – DRAM.
On the memory speed side, we are seeing miss penalty from the last level cache at multiple hundreds of cycles (e.g. 150ns average memory access time in a 4 GHz CPU system is 600+ cycles). This is in the same range as the page fault penalties of early virtual memory systems of the 1960s in number of cycles. Simply using new technologies as replacement of existing hierarchy replacement may not be the most desirable approach. For example, using eDRAM as another level of cache will reduce CPU requests to traditional, off-package DRAM and thus reducing the average memory access time. However it will need large amount of tags and logic to manage the large cache that takes up a substantial amount of space on the CPU chip which could be used to increase the size of the next lower level cache. How would we respond to these changes? How to reconstruct the whole memory sub-system afresh faced with an array of memory technology choices for on-die caches, main memory and storage in the near future? We are particularly interested in new or controversial ideas. Work in early stages of development is encouraged. The workshop will include one or more keynote speakers.