Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010)
Sheraton Station Square
Pittsburgh, PA - March 13~17, 2010
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accepted_papers [2010/03/11 15:01] chensm change affiliations for the two LBA papers to include Intel Labs Pittsburgh |
accepted_papers [2012/01/14 23:36] (current) |
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====== Technical Program ====== | ====== Technical Program ====== | ||
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+ | The [[http://llvm.cs.uiuc.edu/~vadve/asplos10-pcchair-report.pdf | Program Chair's Report]] is now available. | ||
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===== Saturday, March 13, 2010 ===== | ===== Saturday, March 13, 2010 ===== | ||
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**3:00- 3:45. Afternoon break** | **3:00- 3:45. Afternoon break** | ||
- | **6:30- 9:30. Opening Reception and [[acceptedposters | Poster Session]], Conference Hotel** | + | **6:30- 9:30. Opening Reception and [[acceptedposters | Poster Session]], Conference Hotel** (supported by VMware) |
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* Technology for Developing Regions: Moore's Law is Not Enough, //Eric Brewer (University of California, Berkeley)// | * Technology for Developing Regions: Moore's Law is Not Enough, //Eric Brewer (University of California, Berkeley)// | ||
- | **12:10-1:40. Lunch.** | + | **12:10-1:40. Lunch.** (supported in part by AMD and by IBM Research) |
**1:40-2:55. Session 3: Parallel Programming 1 (Session Chair: Yuanyuan Zhou)** | **1:40-2:55. Session 3: Parallel Programming 1 (Session Chair: Yuanyuan Zhou)** | ||
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* Addressing Shared Resource Contention in Multicore Processors Via Scheduling, // Sergey Zhuravlev, Sergey Blagodurov and Alexandra Fedorova (Simon Fraser University)// | * Addressing Shared Resource Contention in Multicore Processors Via Scheduling, // Sergey Zhuravlev, Sergey Blagodurov and Alexandra Fedorova (Simon Fraser University)// | ||
- | **5:30-7:00. Wild and Crazy Ideas (WACI). //Session Chair: Seth Copen Goldstein. (Carnegie Mellon University)//** | + | **5:30-7:00. Wild and Crazy Ideas (WACI). //Session Chair: Seth Copen Goldstein. (Carnegie Mellon University)//** (supported by Google) |
* Short presentations of your best and WACIest ideas. | * Short presentations of your best and WACIest ideas. | ||
- | **7:30- 9:30. Reception, Carnegie Mellon University.** Multiple chartered [[http://www.mollystrolleys.com/PGH_Home.html| Molly's Trolleys]] will make round trips between CMU and Sheraton continuously between 7pm and 10:30pm. | + | **7:30- 9:30. Reception, Carnegie Mellon University.** (supported by Google) Multiple chartered [[http://www.mollystrolleys.com/PGH_Home.html| Molly's Trolleys]] will make round trips between CMU and Sheraton continuously between 7pm and 10:30pm. |
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* Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement, // Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian and Al Davis (University of Utah)// | * Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement, // Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian and Al Davis (University of Utah)// | ||
- | **12:25-1:55 Lunch.** | + | **12:25-1:55 Lunch.** (supported in part by Microsoft and by SUN) |
**1:55-2:45. Session 7. Data Centers (Session Chair: Scott Mahlke)** | **1:55-2:45. Session 7. Data Centers (Session Chair: Scott Mahlke)** | ||
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* Flexible Architectural Support for Fine-grain Scheduling, // Daniel Sanchez, Richard Yoo and Christos Kozyrakis (Stanford University) // | * Flexible Architectural Support for Fine-grain Scheduling, // Daniel Sanchez, Richard Yoo and Christos Kozyrakis (Stanford University) // | ||
- | **6:00-9:30. Banquet, Heinz History Center.** Multiple chartered [[http://www.mollystrolleys.com/PGH_Home.html| Molly's Trolleys]] will make round trips between the Heinz Center and Sheraton continuously between 5:45pm and 10:15pm. | + | **6:00-9:30. Banquet, Heinz History Center.** (supported in part by HP and by Intel) Multiple chartered [[http://www.mollystrolleys.com/PGH_Home.html| Molly's Trolleys]] will make round trips between the Heinz Center and Sheraton continuously between 5:45pm and 10:15pm. |
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* Specifying and Dynamically Verifying Address Translation-Aware Memory Consistency, // Bogdan Romanescu, Alvin Lebeck and Daniel Sorin (Duke University)// | * Specifying and Dynamically Verifying Address Translation-Aware Memory Consistency, // Bogdan Romanescu, Alvin Lebeck and Daniel Sorin (Duke University)// | ||
- | * Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, // Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu and Yale Patt (The University of Texas at Austin)// | + | * Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems, // Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu and Yale Patt (The University of Texas at Austin; Carnegie Mellon University)// |
* An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems, // Isaac Gelado, Javier Cabezas, John Stone, Sanjay Patel, Nacho Navarro and Wen-mei Hwu (University of Illinois at Urbana- Champaign; UPC)// | * An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems, // Isaac Gelado, Javier Cabezas, John Stone, Sanjay Patel, Nacho Navarro and Wen-mei Hwu (University of Illinois at Urbana- Champaign; UPC)// |