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Education
All modern digital systems contain fast, complex computational circuits.
The theory for designing and analyzing the properties of these circuits
is now presented in "Digital Computation" (18-340),
a new undergraduate course that describes the design and analysis of this
important class of circuits. This course explores and develops techniques
for designing high-performance digital circuits for computation along with
methods for evaluating their design attributes such as testability, power
consumption, design and manufacturing cost, timing, and verifiability.
The course
"Digital Systems Testing and Testable Design" (18-765)
is one of the ECE Department's core curriculum of graduate-level CAD courses
in manufacturing, logic design, circuit layout, and simulation. It covers
all topics related to the testing of complex digital systems. Students
complete homework and programming assignments, exams, utilize academic
and industrial CAD tools and equipment, and engage in semester-long projects
that range from implementing test-related CAD tools to developing testing
methodologies for state-of-the-art integrated systems.
Research
The Carnegie Mellon Laboratory for Integrated Systems TEST (CM-LIST)
is focused on developing new test and validation methods for sub-micron
integrated systems that contain high-speed digital, analog and micromechanical
components.
Our work
is focused on four research thrusts:
MEMS
Testing - Dramatic improvements over their conventional counterparts
has increased the demand for microelectromechanical systems (MEMS).
However, successful deployment of new MEMS greatly depends on cost-effective
test methods for detecting defects. Our work in this area focuses on
developing failure models, test generation algorithms, and self-test
design techniques that ensure the end quality of MEMS.
Dynamic
Logic Testing - Most microprocessor companies are now using high-speed
dynamic logic to help achieve extremely fast clocking rates. The design
and manufacturing features that makes dynamic logic circuits fast also
makes them more susceptible to failure. Our work in this area focuses
on developing comprehensive test strategies for various families of
dynamic logic.
True
Hierarchical Test - With very few exceptions, commercial CAD tools
for test operate at the logic gate level of abstraction. The goal of
this research thrust is to develop hierarchical fault simulation and
ATPG algorithms that perform test analysis at every level of the hierarchy
with the capability of precisely relating high-level faults to low-level
misbehaviors.
Microarchitecture
Design Validation -
Formal verification cannot verify all the behavior of a modern microprocessor.
Thus, simulation is universally used to help validate the correctness
of a design. However, the inputs used for simulation are typically generated
in an ad-hoc fashion. In Buffer-Oriented Microarchitecture Validation
(BMV), we utilize ATPG-like test generation techniques to derive test
programs that systematically exercise the control aspects of the microarchitecture.
Links
- Digital
Computation (18-340)
- Digital
Systems Testing and Testable Design (18-765)
- Carnegie
Mellon Laboratory for Integrated Systems TEST (CM-LIST)
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