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LASIC: Layout Analysis for Systematic Identification using Clustering
Wing Chiu Tam |
Osei Poku |
Shawn Blanton |
The relentless scaling of CMOS devices continues to pose formidable challenges to the IC manufacturing community. As the IC manufacturing process becomes more and more complex, its interaction with the design becomes much less predictable. As a result, certain layout features are more difficult to manufacture than others and thus have an increased likelihood of failure. Unlike random defects caused by contaminations, defects due to design-process interaction are systemic in nature. In other words, they can lead to repeated IC failures wherever there are similar layout features. If these yield-limiting layout features can be identified and eliminated, then both yield and quality can be improved. LASIC addresses this problem using a diagnosis-driven approach which is illustrated in Fig. 1. Our physically-aware diagnosis tool (DIAGNOSIX) is applied to a large number of failed ICs to identify the failing locations. An in-house layout analysis tool is then used to extract layout snippets that capture all the failure locations identified from all the failed ICs, where each snippet is stored as a raster image. Clustering, such as K-means, is applied to these images to identify the layout-feature commonalities that may underlie the failure sites. Fig. 2 shows examples of snippet images taken from two different clusters resulting from an actual population of chip failures. Fig. 2 shows that geometries in the same cluster are quite similar but are not exactly the same, while geometries in different clusters exhibit substantial differences. After systematic defects are identified and understood, it is then possible to formulate DFM rules that describe the yield-limiting layout features that cause them. The discovered DFM rules can be implemented and enforced using geometric operations provided by all rule-checking programs (e.g., Mentor Graphics Calibre Pattern Matching). The follow-on analysis involving DFM rules is an important step to complete the feedback loop in yield learning and is the focus of current work.
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Fig 1. Flow diagram implemented in LASIC. |
Fig 2. Illustration of clustered snippets from two different clusters. |
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