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Development of A Process-Aware DFM Framework by Leveraging Test Data
Jonatan Sierra |
Wing Chiu Tam |
Shawn Blanton |
C. Fred Higgs III |
Since deep nanoscale ICs are increasing in complexity and systematic variation, there is a need to transfer more precise actionable hotspot information to the designer earlier in the design cycle to improve yield and performance. Two major contributors to systematic variation are lithography and chemical mechanical polishing (CMP). The goal of this study is to explore layout geometries which have been determined to have faulty nets by evaluating them using a simulated damascene manufacturing process. Layout snippets that contain a faulty net have actually been “virtually fabricated” by performing lithography, etching, deposition, and physics-based CMP manufacturing simulations. Consequently, this approach is able to predict the multi-scale variations due to the processes, namely CMP, without employing the traditional pattern density methods. Since this approach would incorporate the physics of CMP, our ability to predict variation will scale with technology nodes without requiring tuning from extensive design of experiments.
In order to increase the accuracy of the hotspot detection of process variations such as those caused by CMP, this project also leverages test data. CMP hotspot predictions using this methodology are expected to have unprecedented accuracy when combined with an advanced diagnosis methodology, which has been applied to thousands of actual failing chips.
Figure 1 shows a cross section of a snippet of a virtually fabricated chip, where variations in the metal (blue color) are visible in the three magnified segments. Figure 2 shows a cumulative hotspot map resulting from hotspots generated at different layers during chip fabrication.
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Fig. 1: Cross section of snippet showing copper pooling after simulation. |
Fig 2: Cumulative heat map (4 Layers). |
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