Journal Papers   |   Conference Papers   |   Other Papers   |   Patents

Publications


Journal Papers

  1. J. G. Brown and R. D. Blanton, “A Built-In Self-Test and Diagnosis Strategy for Chemically-Assembled Electronic Nanotechnology,” Journal of Electronic Testing: Theory and Applications, vol. 23, no. 2/3 pp. 131–144, June 2007.

  2. R. D. Blanton, K. N. Dwarakanath and R. Desineni, “Fault Modeling using Fault Tuples,” IEEE Transactions on CAD, vol. 25, no. 11, pp. 2450-2464, Nov. 2006.

  3. T. Jiang and R. D. Blanton, “Inductive Fault Analysis of Inertial MEMS,” IEEE Transactions on CAD, vol. 25, no. 6, pp. 1104-1116, June 2006.

  4. S. Biswas and R. D. Blanton, “Statistical Test Compaction Using Binary Decision Trees,” IEEE Design & Test of Computers, vol. 23, no. 6, pp. 452-462, June 2006.

  5. J. E. Nelson, T. Zanon, J. G. Brown, O. Poku, R. D. Blanton, W. Maly, B. Benware and C. Schuermyer, “Extracting Defect Density and Size Distributions from Product ICs,” IEEE Design & Test of Computers, vol. 23, no. 5, pp. 390-400, May 2006.

  6. N. Deb and R. D. Blanton, “Built-in Self Test of MEMS Accelerometers,” IEEE Journal of Microelectromechanical Systems,” vol. 15, no. 1, pp. 52-68, Feb. 2006.

  7. R. D. Blanton and J. P. Hayes, “On the Properties of the Input Pattern Fault Model,” ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 1, pp. 1–17, Jan. 2003.

  8. K. Heeragu, M. Sharma, R. Kundu and R. D. Blanton, “Test Vector Generation for Charge Sharing Failures in Dynamic Logic,” IEEE Transactions on Computer-Aided Design, vol. 21, no. 12, pp. 1502–1508, Dec. 2002.

  9. R. Arunachalam, R. D. Blanton and L. T. Pileggi, “Accurate Coupling-Centric Timing Analysis Incorporating Temporal and Functional Isolation,” VLSI Design (Special Issue on Timing Analysis and Optimization for DSM ICs), vol. 15, pp. 605-618, 2002.

  10. P. K. Nag, S. Wei, A. Gattiker, R. D. Blanton and W. Maly, “Modeling Economics of Testing: A DFT Perspective,” IEEE Design & Test of Computers, vol. 19, no. 1, pp. 29–41, Jan./Feb. 2001.

  11. N. Deb, S. Iyer, T. Mukherjee and R. D. Blanton, “MEMS Resonator Synthesis for Defect Reduction,” Applied Computational Research Society (ACRS) Journal of Modeling and Simulation of MEMS, vol. 2, no. 1, pp. 11–20, 2001.

  12. N. Deb and R. D. Blanton, “High-Level Fault Modeling in Surface-Micromachined MEMS,” Kluwer Journal on Analog Integrated Circuits and Signal Processing, vol. 29, no. 1/2, pp. 151–158, Oct./Nov. 2001.

  13. N. Utamaphethai, R. D. Blanton and J. P. Shen, “On the Effectiveness of Microarchitecture Test Program Generation,” IEEE Design & Test of Computers, vol. 17, no. 4, pp. 38–49, Sept.-Dec. 2000.

  14. R. D. Blanton and J. P. Hayes, “On the Design of Fast, Easily Testable ALUs,” IEEE Transactions on VLSI Systems, vol. 8, no. 2, pp. 220–223, April 2000.

  15. N. Utamaphethai, R. D. Blanton and J. P. Shen, “A Buffer-Oriented Methodology for Microarchitecture Validation,” Journal of Electronic Testing: Theory and Applications, vol. 16, no. 1/2, pp. 49–65, Feb. 2000.

  16. T. Mukherjee, R. D. Blanton and G. K. Fedder, “Hierarchical Design and Test of Integrated Microsystems,” IEEE Design & Test of Computers, pp. 18–27, vol. 16, no. 4, Oct.-Dec. 1999.

  17. A. Kolpekwar, T. Jiang and R. D. Blanton, “CARAMEL: Contamination and Reliability Analysis of Microelectromechanical Layout,” IEEE Journal of Microelectromechanical Systems, vol. 8, no. 3, pp. 1–10, Sept. 1999.

  18. C. Bechem, J. Combs, N. Utamaphethai, B. Black, R. D. Blanton and J. P. Shen, “An Integrated Functional Performance Simulator,” IEEE Micro, pp. 26–35, May-June 1999.

  19. R. D. Blanton and J. P. Hayes, “Testability of Divergent Tree Circuits,” Journal of Electronic Testing, no. 11, pp. 197-209, Dec. 1997.

  20. R. D. Blanton and J. P. Hayes, “Testability of Convergent Tree Circuits,” IEEE Transactions on Computers, vol. 45, no. 8, pp. 950–963, Aug. 1996.