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Graduated Ph.D. Students

Rahul Kundu

Rahul Kundu

Thesis Title: Test Generation for Noise-Induced Failures in Domino Logic Circuits, Feb. 2003
Current Employer: Intel Corporation, Santa Clara, CA
Current Title: Staff CAD Engineer, Design Technology Solutions

  

Noppanunt Utamaphethai

 intel

Noppanunt Utamaphethai

Thesis Title: Buffer-Oriented Microarchitecture Design Verification, June  2003
Current Employer: Intel Corporation, Austin, TX
Current Title: Formal Verification Technical Lead, Ultra Mobile Platform Group
Kumar Dwarakanath intel

Kumar Dwarakanath

Thesis Title: Fault Tuples: Theory and Applications, Sept. 2003
Current Employer: Intel Corporation, Folsom, CA
Current Title: Component Design Engineer

   Nilmoni Deb intel

Nilmoni Deb

Thesis Title: Defect-Oriented Test of Inertial Microsystems, Oct. 2004
Current Employer: Intel Corporation, Austin, TX
Current Title: Component Design Engineer
Rao Desineni Global Foundries

Rao Desineni

Thesis Title: A Comprehensive Diagnosis Methodology for Characterizing Logic-Behavior of IC Failures, April 2006
Current Employer: Globalfoundries, Malta, NY
Current Title: Senior Manager, Technology & Integration Engineering

   Jason Brown intel

Jason Brown

Thesis Title: Exploiting Regularity for Defect-Based Test, Dec. 2008
Current Employer: Intel Corporation, Hillsboro, OR
Current Title: Software Engineer
Sounil Biswas nvidia

Sounil Biswas

Thesis Title: Reducing Test Execution Cost of Integrated, Heterogeneous Systems through Data Mining, Dec. 2008
Current Employer: Nvidia Corporation, Hillsboro, OR
Current Title: Senior Hardware Engineer

   Iris Lin nvidia

Yen-Tzu Lin

Thesis Title: Physically-Aware N-Detect Test, May 2010
Current Employer: Nvidia Corporation, Santa Clara, CA
Current Title: Hardware Engineer
Jeff Nelson ibm

Jeff Nelson

Thesis Title: Using Integrated Circuits as Virtual Test Structures
to Extract Defect Density and Size Distributions, Aug. 2010
Current Employer: IBM Corporation, Fishkill, NY
Current Title: Characterization Engineer, 300mm Diagnostics Characterization

   Xiao Chun Yu intel logo

Xiaochun Yu

Thesis Title: Controlling IC Quality through Diagnosis Based Adaptive Test, May. 2011
Current Employer: Intel Corporation, Hillsboro, OR
Current Title: Software Engineer

 

Graduated M.S. Students

Sichao (Sam) Wei
  • Project Title: Economics of Design for Testability, Sept. 1997.
  • Current Employer: Two Sigma
Abhijeet Kolpekwar
  • Project Title: Development of a MEMS Testing Methodology, May 1998.
  • Current Employer: Cadence Design Systems
Tao Jiang
  • Project Title: MEMS Fault Modeling, May 2000.
  • Current Employer: Freescale Semiconductor
Sunil Montaparti
  • Project Title: Redundant Fault Identification, May 2004.
  • Current Employer: KeyPoint Technologies
Naresh Bhatti
  • Project Title: TG-FAD: A Diagnostic Test Generator for Arbitrary Defects, Aug. 2006.
  • Current Employer: Mentor Graphics
Anupama Suryanarayanan
  • Project Title: CANOPY: A Hierarchical Approach to Fast and Efficient Classification using Decision Trees, Dec. 2009
  • Current Employer: Intel
Prajna Shetty
  • Project Title: Using SLAT to Analyze Non-SLAT Failure Patterns, Dec. 2010
  • Current Employer: Apple
Thomas Tzou
  • Project Title: Automatic Fault Generation; Physically-Aware Netlists, May 2011
  • Current Employer: IBM

Former Undergraduate Students

  1. Raman Sharma, “IDDQ Test Generation for Regular Circuits,” Spring 1996.
  2. Anuj Agarwal, “ATPG for Regular Circuits,” Summer 1996.
  3. Prakash Guda, “FSM Test Generation,” Spring 1997.
  4. Brian Prasky, “ATPG for One ¬Dimensional Arrays,” Summer 1998.
  5. Nathan Drees, “On the Understanding of Crosstalk on Dynamic Logic Misbehavior,” Summer 1999.
  6. John Gunter, “On the Understanding of Bridging Shorts on Dynamic Logic Misbehavior,” Summer 1999.
  7. Michelle Kruvczuk, “Manufacturing Corner Analysis of New Dynamic Logic Families,” Summer 1999.
  8. Adrian Drury, “Testing Digital Circuits on the Teradyne J941 VLSI IC Tester,” Summer 1999.
  9. Reena Singhal, “Test Cost Modeling,” Spring 2000.
  10. Michael Menietti, “BIST via Ring Counters,” Fall 2000 and Spring 2001.
  11. Anirudh Shah, “Layout-based Neighbor Identification,” Fall 2002 and Spring 2003.
  12. Emiko Oforitsenere, “Economic Yield Recovery Model for VPGA,” Spring 2003.
  13. Nishant Patil, “Macrofault Modeling of Spot¬ Contamination Induced Bridge Defects,” Fall 2004.
  14. Derrick Losli, “Salvaging ALU Functionality via Behavioral Failure Diagnosis,” Spring and Fall 2007.
  15. Henry Teng, “Statistical Analysis of Test Data,” NSF REU, Summer 2007.
  16. Ibrahima Komara, “Sensitivity Analysis of Diagnosis Accuracy on Fail Data Volume,” NSF REU, Summer 2009.
  17. Vincent Liu, “Sensitivity Analysis of Diagnosis Accuracy on Fail Data Volume,” NSF REU, Summer 2010.
  18. Shonda Bell, “Physically-Aware Netlists,” NSF REU, Summer 2010.
  19. Thomas Tzou, “Automatic Macrofault Generators,” NSF REU, Spring and Summer 2010.
  20. Martyn Romanko, “Fault Detection, Diagnosis, and Tolerance within ALUs,” Summer 2010.
  21. Idryiys Harris, “Web-based Interface for Virtual Fail Data,” Summer 2011.
  22. Suryavanshi Saurabh, “Trojan Detection in FPGAs,” Summer 2011.