Fall 2009
Motivations: On-chip network has become a critical communication component for most modern multiprocessor for data transport. For research purposes on architectural exploration and software development, many simulators have been built in order simulate large multiprocessor systems with a large number of processors. However, most of the simulation tools are software-based which has limited throughput on simulating large models. My objective is to build an on-chip network simulator as an instrumentation to BlueSPARC which is an FPGA-based full-system functional simulator for a 16-way UltraSPRAC III SMP multiprocessor server.
Method: In order to represent an accurate packets flow in the network, a mesh of routers can be utilized to simulate the flow. The network will be using deterministic dimensional-order routing, which is the routing method being used by most of the multiprocessor systems. The pipeline router architecture will have the following components: channel buffers, virtual channels, and crossbar switch. The router will also modules to perform route-computation, virtual-channel allocation and switch allocation. In order to give the users a clear representation of the flow congestion in each particular router, the simulator will use the buffers occupancy as an indication.