Documentation

ProtoFlex is a simulation architecture, which uses FPGAs to accelerate full system multiprocessor simulation and to facilitate high-performance instrumentation. Prior FPGA approaches that prototype a complete system in hardware are either too complex when scaling to large-scale configurations or require significant effort to provide full-system support. In contrast, ProtoFlex virtualizes the execution of many logical processors onto a consolidated number of multiple-context execution engines on the FPGA. Through virtualization, the number of engines can be judiciously scaled, as needed, to deliver on necessary simulation performance at a large savings in complexity. Further, to achieve low-complexity full-system support, a hybrid simulation technique called transplanting allows implementing in the FPGA only the frequently encountered behaviors, while a software simulator preserves the abstraction of a complete system.

BlueSPARC is a full-system FPGA-based simulator that models the architectural behavior of a 16-CPU UltraSPARC III SMP server and embodies the two key concepts of the ProtoFlex simulation architecture: time-multiplexed interleaving and hybrid simulation with transplanting.

The source code of BlueSPARC is organized according to the following directory structure:

• build: contains generated Verilog files. (This will eventually contain all necessary files to compile the project.)
• include: containsC include files for the PowerPC. The generate_types.sh script creates mirrored type-definitions.
• lib: These are Bluespec-related Verilog primitives.
• logs: date-stamped compile logs
• obj: Contains intermediate generated files (e.g. *.bi *.bo *.ba). This will eventually contain all necessary files to compile the project.
• scripts:
  • check_warns.sh: Will go through entire source code and check for “TODO” or “FIX_ME” flags.
  • compile_vcs.sh: Will generate self-contained VCS simulation.
  • compile_xst.sh: Will generate self-containted script to synthesize project using XST.
  • Rest of scripts probably deprecated
• rtl: Contains all Bluespec and Verilog rtl source code.