====== ProtoFlex ====== ProtoFlex is an FPGA-accelerated hybrid functional simulator designed to advance large-scale multiprocessor hardware and software research. ProtoFlex provides first-class support for full-system fidelity–i.e., the ability to run stock commercial operating systems with I/O support. This is accomplished without undue effort by leveraging a hybrid emulation technique called transplanting. Our transplant technology uses FPGAs to dynamically accelerate only common-case behaviors while relegating infrequent, complex behaviors (e.g., I/O devices) to software simulation. By working in concert with existing full-system simulators, transplanting avoids the costly and unnecessary construction of the entire target system in FPGA. At present, we are targeting SPARCV9 and x86 platforms. {{:pflex-tplant.jpg|Protoflex Transplanting}} We are also developing a novel multiprocessor emulation approach that interleaves the execution of many (10s to 100s) processor contexts onto a shared emulation engine. This approach decouples the scale and complexity of the FPGA host from the simulated system size but nevertheless enables us to scale the desired emulation performance by the number of emulation engines used. Together, the transplant and interleaving techniques enable us to develop full-system FPGA emulators of up to thousands of processors without an overwhelming development effort. Lastly, ProtoFlex complements sampling-based methodologies (SMARTS) by reducing one of the key bottlenecks in cycle-accurate simulation turnaround-time. The functional ProtoFlex emulator can be fully instrumented—with virtually no slowdown—to conduct functional warming of long-term microarchitectural structures (e.g., caches, branch predictors). The level of performance and scalability offered would permit practical cycle-accurate simulation studies of systems at a much larger scale than possible today with software simulation. {{:pflex-mp.jpg|Protoflex Host Multithreading}} \\ \\ ---- **Faculty:** [[http://www.ece.cmu.edu/~jhoe|James C. Hoe]], [[http://www.ece.cmu.edu/~babak|Babak Falsafi]], [[http://www.ece.cmu.edu/directory/details/298/|Ken Mai]]\\ **Students:** [[http://www.ece.cmu.edu/~echung|Eric S. Chung]], [[http://www.cs.cmu.edu/~mpapamic|Michael K. Papamichael]], [[http://www.ece.cmu.edu/~bgold|Brian Gold]], [[http://www.ece.cmu.edu/~enurvita|Eriko Nurvitadhi]]\\ **Related links:** [[http://www.ece.cmu.edu/~simflex|SimFlex]], [[http://www.virtutech.com/|Virtutech Simics]], [[http://ramp.eecs.berkeley.edu/|RAMP]], [[http://bee2.eecs.berkeley.edu/|BEE2]]\\ ---- \\ ===== Instructions for obtaining the source code ===== To get a copy of the source code and view instructions on how to use Protoflex, please visit the **[[documentation:userguide|User Guide]]**. \\ \\ ===== Publications ===== **{{:a15-chung.pdf|ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs}}**\\ Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai.\\ //ACM Transactions on Reconfigurable Technology and Systems//, 2009.\\ \\ **{{:fpga08-chung.pdf|A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs}}**\\ Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai.\\ //International Symposium on Field Programmable Gate Arrays//, February 2008, Monterey, CA.\\ \\ **{{:chung_warp2007_final.pdf|Virtualized Full-System Emulation of Multiprocessors using FPGAs}}**\\ Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai.\\ //2nd Workshop on Architectural Research Prototyping held in conjunction with the 34th International Symposium on Computer Architecture, June 2007, San Diego, CA.//\\ \\ **{{:calcm_tr_2007-2.pdf|ProtoFlex: FPGA-accelerated Hybrid Functional Simulation}}**\\ Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai.\\ //CALCM Technical Report 2007-2, February 2007//\\ \\ **{{:warfp2006.pdf|ProtoFlex: Co-Simulation for Component-wise FPGA Emulator Development}}**\\ Eric S. Chung, James C. Hoe, and Babak Falsafi\\ In the //2nd Workshop on Architecture Research using FPGA Platforms (WARFP 2006)//, February 2006\\ \\ **{{:warfp05.pdf|Full-system Architectural Exploration Sandbox}}**\\ Eriko Nurvitadhi and James C. Hoe\\ In the //First Workshop on Architecture Research using FPGA Platforms (WARFP 2005)//, February 2005\\ \\ ===== Recent Talks ===== **{{:ramp_retreat_aug_2008.pdf|Protoflex: FPGA-Accelerated Instrumentation}}**\\ Michael K. Papamichael, Eric S. Chung, James C. Hoe, Babak Falsafi, Ken Mai.\\ Given at the //RAMP Summer Retreat//, August 2008\\ \\ **{{:pflex-ramp-07.ppt|ProtoFlex: FPGA-accelerated Hybrid Functional Simulator}}**\\ Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai.\\ Given at the //RAMP Winter Retreat//, January 2007\\ \\ **{{:pflex-ramp-06.ppt|Combining Simulators and FPGAs: "An Out-of-Body Experimence"}}**\\ Eric S. Chung, Brian Gold, James C. Hoe, Babak Falsafi\\ Given at the //RAMP Summer Retreat//, June 2006\\ \\ **{{:x86-ramp-06.ppt|Building a Synthesizable x86}}**\\ Eriko Nurvitadhi, James C. Hoe, Babak Falsafi\\ Given at the //RAMP Summer Retreat//, June 2006\\ \\ ===== Recent Posters ===== **{{:RAMP_Retreat_Jan_2010_poster.pdf|The Open-Source ProtoFlex Simulator}}**\\ Eric S. Chung, Michael K. Papamichael, James C. Hoe, Ken Mai, Babak Falsafi.\\ Presented at the //RAMP Winter Retreat//, January 2010\\ \\ **{{:ASPLOS_2008_poster.pdf|An MP Architectural Exploration Vehicle Using Complexity-Effective FPGA-Accelerated Simulation}}**\\ Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai.\\ Presented at //ASPLOS 2008//, March 2008\\ \\ **{{:RAMP_Retreat_Aug_2008_poster.pdf|Protoflex: Complexity-Effective FPGA-Accelerated Instrumentation}}**\\ Michael K. Papamichael, Eric S. Chung, James C. Hoe, Babak Falsafi, Ken Mai.\\ Presented at the //RAMP Summer Retreat//, August 2008\\ \\ \\ ---- This research is currently supported in funding and/or equipment by **NSF** (Award--0811702), **FCRP**/**C2S2**, **SUN**, and **Xilinx**.