Memory Architecture in Multicore

Summer-1/All 2011

Student
Chan Sik Kim
Advisor
James Hoe
Project description

Numerous techniques have been developed to reduce TLB miss penalty in uniprocessors, including the impact of TLB size, associativity, multilevel hierarchies, super pages, and prefetching. TLB design and optimizations for multiprocessors are currently being actively research. In this project, I will first review and recreate the results from recent papers on TLB optimizations. I will continue by proposing and evaluating my own enhancements in this space.

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