Evaluating the Effect of Layout Regularity on Circuit Performance

Spring 2011

Student
Volkan Eren
Advisor
Andrzej Strojwas
Project description

We minimized the number of unique layout patterns in a 45nm regular fabric-based standard cell library. The pattern count can be improved by restricting layout shapes at cell boundaries, adding pattern fill (non-functional layout shapes), and decreasing within cell layout complexity. We will evaluate the effect of different layout patterns on performance while considering the number of patterns in layout. Different layout patterns consist of varying types of dummy fills. Our eventual goal will be to determine which dummies contributed the most to the performance penalty and what the optimum layout should be.

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