In this project, I would like to continue my research work with Professor Mai and his group from this summer. We worked on developing new, low-cost, low-overhead countermeasures against invasive and non-invasive attacks for embedded systems and field-programmable gate-arrays (FPGAs.) These include: new logic families that have constant power dissipation yet incur low area and power costs; novel memory circuits to avoid leaving remnants of past stored data; and techniques to use reconfigurability to enhance the security beyond even that dedicated custom secureICs. In particular, the work I did this summer was to create ring oscillator chains to monitor the process of the AES encryption circuit. I made several chains of various gates of various fan-outs. Over the course of the summer project, I completed cadence schematics for inverter, nand, and nor chains of fan-outs ranging from 1 to 8. By continuing this work in the fall semester, I will need to design the layout for the ring oscillator chains using cadence layout tools.