The objective of this project is to design and develop 16-bit floating-point adder and multiplier softcores for the Xilinx Virtex-4 FPGAs. For this project, a 5-bit exponent field with a 10-bit fraction field will be used. The floating point arithmetic flow chart will be using the one in H&P Computer Organization and Design textbook, and probably modified at the end. All logic circuit would be written in Verilog, and the library should be synthesizable for the Xilinx Virtex-4 FPGAs. The results will be evaluated and compared to the Xilinx LogiCORE floating-point arithmetic library in the aspects of speed and size. The goal of this project is to develop floating-point arithmetic IPs for hardware DSP transform implementations generated by the SPIRAL compiler. At the completion of the project, a 30-minnute presentation will be given in the SPIRAL group meeting.