Undergrad Research Project - Phase-Locked Loop Design

Spring 2016

Student
Jess Chernak
Advisor
Jeyanandh Paramesh
Project description

I am working with Professor Paramesh and a graduate student of his on their design for a new phase-locked loop (PLL) integrated circuit. The chip is planned to be taped-out later this spring. I will be primarily handling aspects such as power supply and regulation. The chip needs a steady voltage supply when drawing a fair amount of power, so determining the best method for providing this can pose a challenge. I will conduct research about various topologies of such circuits, their benefits and drawbacks, and run experiments on several different layouts. The team will then select the appropriate design and use it to power the chip.

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